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LINE 63
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T10,T89,T91 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 75
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T14,T15,T16 |
| 1 | 0 | Covered | T91,T93,T95 |
LINE 82
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T14,T15,T16 |
| 0 | 1 | 0 | Covered | T91,T93,T95 |
| 1 | 0 | 0 | Covered | T91,T93,T95 |
LINE 130
EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[4096:6143]}) ? 1'b0 : 1'b1)
------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 168
EXPRESSION (addrmiss | wr_err | intg_err)
----1--- ---2-- ----3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T91,T93,T95 |
| 0 | 1 | 0 | Covered | T10,T89,T92 |
| 1 | 0 | 0 | Covered | T10,T89,T90 |
LINE 989
EXPRESSION (direct_access_cmd_we & direct_access_regwen_qs)
----------1--------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 1042
EXPRESSION (direct_access_address_we & direct_access_regwen_qs)
------------1----------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T5 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 1074
EXPRESSION (direct_access_wdata_0_we & direct_access_regwen_qs)
------------1----------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T2,T3,T9 |
LINE 1106
EXPRESSION (direct_access_wdata_1_we & direct_access_regwen_qs)
------------1----------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T8 |
| 1 | 1 | Covered | T2,T3,T9 |
LINE 1202
EXPRESSION (check_trigger_we & check_trigger_regwen_qs)
--------1------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T21 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1267
EXPRESSION (check_timeout_we & check_regwen_qs)
--------1------- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T9,T8,T6 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1298
EXPRESSION (integrity_check_period_we & check_regwen_qs)
------------1------------ -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T91,T93,T94 |
| 1 | 1 | Covered | T206,T90,T91 |
LINE 1329
EXPRESSION (consistency_check_period_we & check_regwen_qs)
-------------1------------- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T91,T93,T94 |
| 1 | 1 | Covered | T206,T90,T91 |
LINE 1360
EXPRESSION (vendor_test_read_lock_we & direct_access_regwen_qs)
------------1----------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T146,T13,T151 |
LINE 1391
EXPRESSION (creator_sw_cfg_read_lock_we & direct_access_regwen_qs)
-------------1------------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T13,T151,T194 |
LINE 1422
EXPRESSION (owner_sw_cfg_read_lock_we & direct_access_regwen_qs)
------------1------------ -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T8 |
| 1 | 1 | Covered | T146,T13,T193 |
LINE 1692
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1693
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1694
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET)
----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T19,T21,T47 |
LINE 1695
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T11,T21 |
LINE 1696
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1697
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_0_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1698
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_1_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1699
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_2_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T9 |
LINE 1700
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_3_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T9 |
LINE 1701
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_4_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1702
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_5_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T9 |
LINE 1703
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_6_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1704
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_7_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T9 |
LINE 1705
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_8_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1706
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_9_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T9 |
LINE 1707
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET)
----------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1708
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1709
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1710
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1711
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1712
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1713
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1714
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET)
----------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1715
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET)
------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T9 |
LINE 1716
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1717
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET)
------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1718
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET)
-----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T33,T21,T47 |
LINE 1719
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET)
------------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T19,T33,T21 |
LINE 1720
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1721
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET)
------------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1722
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET)
-----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T8 |
LINE 1723
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET)
----------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1724
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET)
----------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1725
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET)
-----------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1726
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET)
-----------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1727
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1728
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1729
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG0_DIGEST_0_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1730
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG0_DIGEST_1_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1731
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1732
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1733
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1734
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1735
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1736
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T4 |
LINE 1739
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1739
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 1743
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[44] & ((|(4'b1111 & (~reg_be)))))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T10,T89,T92 |
LINE 1743
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b1 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b1 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b1 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b1 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b1 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b1 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b1 & (~reg_be))))) |
9 (addr_hit[8] & ((|(4'b1 & (~reg_be))))) |
10 (addr_hit[9] & ((|(4'b1 & (~reg_be))))) |
11 (addr_hit[10] & ((|(4'b1 & (~reg_be))))) |
12 (addr_hit[11] & ((|(4'b1 & (~reg_be))))) |
13 (addr_hit[12] & ((|(4'b1 & (~reg_be))))) |
14 (addr_hit[13] & ((|(4'b1 & (~reg_be))))) |
15 (addr_hit[14] & ((|(4'b1 & (~reg_be))))) |
16 (addr_hit[15] & ((|(4'b1 & (~reg_be))))) |
17 (addr_hit[16] & ((|(4'b1 & (~reg_be))))) |
18 (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) |
19 (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) |
20 (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) |
21 (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) |
22 (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) |
23 (addr_hit[22] & ((|(4'b1 & (~reg_be))))) |
24 (addr_hit[23] & ((|(4'b1 & (~reg_be))))) |
25 (addr_hit[24] & ((|(4'b1 & (~reg_be))))) |
26 (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) |
27 (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) |
28 (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) |
29 (addr_hit[28] & ((|(4'b1 & (~reg_be))))) |
30 (addr_hit[29] & ((|(4'b1 & (~reg_be))))) |
31 (addr_hit[30] & ((|(4'b1 & (~reg_be))))) |
32 (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) |
33 (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) |
34 (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) |
35 (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) |
36 (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) |
37 (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) |
38 (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) |
39 (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) |
40 (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) |
41 (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) |
42 (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) |
43 (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) |
44 (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) |
45 (addr_hit[44] & ((|(4'b1111 & (~reg_be))))))
| Sensitive Expression == 1 | Status | Tests |
|---|
| ALL ZEROS | Covered | T1,T2,T3 |
| 45 (addr_hit[44] & ((|(4'... | Covered | T1,T9,T5 |
| 44 (addr_hit[43] & ((|(4'... | Covered | T1,T9,T5 |
| 43 (addr_hit[42] & ((|(4'... | Covered | T1,T9,T5 |
| 42 (addr_hit[41] & ((|(4'... | Covered | T1,T9,T5 |
| 41 (addr_hit[40] & ((|(4'... | Covered | T1,T9,T4 |
| 40 (addr_hit[39] & ((|(4'... | Covered | T1,T9,T4 |
| 39 (addr_hit[38] & ((|(4'... | Covered | T1,T9,T4 |
| 38 (addr_hit[37] & ((|(4'... | Covered | T1,T9,T5 |
| 37 (addr_hit[36] & ((|(4'... | Covered | T1,T9,T4 |
| 36 (addr_hit[35] & ((|(4'... | Covered | T1,T9,T4 |
| 35 (addr_hit[34] & ((|(4'... | Covered | T1,T9,T4 |
| 34 (addr_hit[33] & ((|(4'... | Covered | T1,T9,T4 |
| 33 (addr_hit[32] & ((|(4'... | Covered | T1,T9,T4 |
| 32 (addr_hit[31] & ((|(4'... | Covered | T1,T9,T4 |
| 31 (addr_hit[30] & ((|(4'... | Covered | T6,T29,T21 |
| 30 (addr_hit[29] & ((|(4'... | Covered | T29,T21,T146 |
| 29 (addr_hit[28] & ((|(4'... | Covered | T4,T19,T21 |
| 28 (addr_hit[27] & ((|(4'... | Covered | T19,T33,T21 |
| 27 (addr_hit[26] & ((|(4'... | Covered | T33,T21,T47 |
| 26 (addr_hit[25] & ((|(4'... | Covered | T21,T47,T146 |
| 25 (addr_hit[24] & ((|(4'... | Covered | T21,T63,T163 |
| 24 (addr_hit[23] & ((|(4'... | Covered | T21,T63,T163 |
| 23 (addr_hit[22] & ((|(4'... | Covered | T1,T19,T146 |
| 22 (addr_hit[21] & ((|(4'... | Covered | T1,T2,T3 |
| 21 (addr_hit[20] & ((|(4'... | Covered | T1,T2,T3 |
| 20 (addr_hit[19] & ((|(4'... | Covered | T3,T6,T21 |
| 19 (addr_hit[18] & ((|(4'... | Covered | T1,T4,T33 |
| 18 (addr_hit[17] & ((|(4'... | Covered | T1,T3,T5 |
| 17 (addr_hit[16] & ((|(4'... | Covered | T1,T19,T5 |
| 16 (addr_hit[15] & ((|(4'... | Covered | T1,T9,T4 |
| 15 (addr_hit[14] & ((|(4'... | Covered | T1,T3,T9 |
| 14 (addr_hit[13] & ((|(4'... | Covered | T1,T9,T4 |
| 13 (addr_hit[12] & ((|(4'... | Covered | T1,T9,T4 |
| 12 (addr_hit[11] & ((|(4'... | Covered | T1,T9,T4 |
| 11 (addr_hit[10] & ((|(4'... | Covered | T1,T9,T4 |
| 10 (addr_hit[9] & ((|(4'b... | Covered | T1,T9,T4 |
| 9 (addr_hit[8] & ((|(4'b... | Covered | T1,T9,T4 |
| 8 (addr_hit[7] & ((|(4'b... | Covered | T1,T3,T9 |
| 7 (addr_hit[6] & ((|(4'b... | Covered | T1,T9,T4 |
| 6 (addr_hit[5] & ((|(4'b... | Covered | T1,T9,T4 |
| 5 (addr_hit[4] & ((|(4'b... | Covered | T1,T2,T3 |
| 4 (addr_hit[3] & ((|(4'b... | Covered | T1,T21,T63 |
| 3 (addr_hit[2] & ((|(4'b... | Covered | T19,T21,T146 |
| 2 (addr_hit[1] & ((|(4'b... | Covered | T1,T180,T231 |
| 1 (addr_hit[0] & ((|(4'b... | Covered | T2,T3,T17 |
LINE 1743
SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T17 |
LINE 1743
SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T180,T231 |
LINE 1743
SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T21,T47,T74 |
| 1 | 1 | Covered | T19,T21,T146 |
LINE 1743
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T11,T21,T12 |
| 1 | 1 | Covered | T1,T21,T63 |
LINE 1743
SUB-EXPRESSION (addr_hit[4] & ((|(4'b0111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 1743
SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1743
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1743
SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T3,T9 |
LINE 1743
SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T9 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1743
SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1743
SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T9 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1743
SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1743
SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T9 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1743
SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1743
SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T3,T9 |
LINE 1743
SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1743
SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T19,T5 |
LINE 1743
SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T5 |
LINE 1743
SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T4,T33 |
LINE 1743
SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T3,T6,T21 |
LINE 1743
SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 1743
SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 1743
SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T19,T146 |
LINE 1743
SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T9 |
| 1 | 1 | Covered | T21,T63,T163 |
LINE 1743
SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T21,T63,T163 |
LINE 1743
SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T21,T47,T146 |
LINE 1743
SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T10,T206,T90 |
| 1 | 1 | Covered | T33,T21,T47 |
LINE 1743
SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T47,T10,T206 |
| 1 | 1 | Covered | T19,T33,T21 |
LINE 1743
SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T4,T19,T21 |
LINE 1743
SUB-EXPRESSION (addr_hit[29] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T29,T21,T146 |
LINE 1743
SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T8 |
| 1 | 1 | Covered | T6,T29,T21 |
LINE 1743
SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1743
SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1743
SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1743
SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1743
SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1743
SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1743
SUB-EXPRESSION (addr_hit[37] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T9,T5 |
LINE 1743
SUB-EXPRESSION (addr_hit[38] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T5 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1743
SUB-EXPRESSION (addr_hit[39] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T5 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1743
SUB-EXPRESSION (addr_hit[40] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T9,T4 |
LINE 1743
SUB-EXPRESSION (addr_hit[41] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T9,T5 |
LINE 1743
SUB-EXPRESSION (addr_hit[42] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T9,T5 |
LINE 1743
SUB-EXPRESSION (addr_hit[43] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T9,T5 |
LINE 1743
SUB-EXPRESSION (addr_hit[44] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T4 |
| 1 | 1 | Covered | T1,T9,T5 |
LINE 1792
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T10,T89,T92 |
| 1 | 1 | 1 | Covered | T2,T3,T9 |
LINE 1797
EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T10,T89,T92 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1802
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T19,T21,T47 |
| 1 | 1 | 0 | Covered | T10,T89,T94 |
| 1 | 1 | 1 | Covered | T10,T275,T114 |
LINE 1807
EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T11,T21 |
| 1 | 1 | 0 | Covered | T10,T92,T276 |
| 1 | 1 | 1 | Covered | T11,T12,T202 |
LINE 1818
EXPRESSION (addr_hit[4] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1819
EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T9,T4 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T9,T4 |
LINE 1820
EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T9,T4 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T9,T4 |
LINE 1821
EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T3,T9 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T9,T4 |
LINE 1822
EXPRESSION (addr_hit[8] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T9 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T9 |
LINE 1823
EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1824
EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T9 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T9 |
LINE 1825
EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1826
EXPRESSION (addr_hit[12] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T3,T9 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T3,T9 |
LINE 1827
EXPRESSION (addr_hit[13] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T9,T4 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T9,T4 |
LINE 1828
EXPRESSION (addr_hit[14] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T3,T9 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T9,T4 |
LINE 1829
EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T9,T4 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T9,T4 |
LINE 1830
EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T10,T89,T134 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1837
EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T10,T97,T277 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1840
EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T10,T92,T97 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1843
EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T10,T89,T92 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1846
EXPRESSION (addr_hit[20] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1847
EXPRESSION (addr_hit[21] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1848
EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T9,T4 |
| 1 | 1 | 0 | Covered | T10,T134,T277 |
| 1 | 1 | 1 | Covered | T1,T9,T4 |