Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.47 91.60 89.36 85.02 79.05 91.53 95.59 73.13


Total test records in report: 722
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T546 /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.2864025576 Jan 24 09:14:36 PM PST 24 Jan 24 09:14:42 PM PST 24 714940157 ps
T547 /workspace/coverage/default/18.otp_ctrl_smoke.2290355786 Jan 24 08:58:06 PM PST 24 Jan 24 08:58:15 PM PST 24 179312413 ps
T548 /workspace/coverage/default/245.otp_ctrl_init_fail.2482975776 Jan 24 09:15:38 PM PST 24 Jan 24 09:15:44 PM PST 24 163433517 ps
T549 /workspace/coverage/default/18.otp_ctrl_regwen.1772038663 Jan 24 09:15:31 PM PST 24 Jan 24 09:15:36 PM PST 24 421043996 ps
T550 /workspace/coverage/default/42.otp_ctrl_smoke.4022841693 Jan 24 09:03:35 PM PST 24 Jan 24 09:03:40 PM PST 24 330474218 ps
T221 /workspace/coverage/default/7.otp_ctrl_smoke.2364922931 Jan 24 08:55:20 PM PST 24 Jan 24 08:55:29 PM PST 24 1569231436 ps
T551 /workspace/coverage/default/71.otp_ctrl_init_fail.1967759603 Jan 24 09:08:40 PM PST 24 Jan 24 09:08:46 PM PST 24 147769124 ps
T552 /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.1562110285 Jan 24 09:10:56 PM PST 24 Jan 24 09:11:01 PM PST 24 147962990 ps
T553 /workspace/coverage/default/60.otp_ctrl_init_fail.3055353906 Jan 24 10:03:13 PM PST 24 Jan 24 10:03:18 PM PST 24 163005803 ps
T554 /workspace/coverage/default/11.otp_ctrl_init_fail.3976829620 Jan 24 08:56:41 PM PST 24 Jan 24 08:56:46 PM PST 24 467350389 ps
T555 /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.3153628513 Jan 24 09:11:53 PM PST 24 Jan 24 09:12:02 PM PST 24 302911611 ps
T556 /workspace/coverage/default/11.otp_ctrl_smoke.770350793 Jan 24 09:06:47 PM PST 24 Jan 24 09:06:53 PM PST 24 356600507 ps
T557 /workspace/coverage/default/47.otp_ctrl_smoke.4152717365 Jan 24 09:06:48 PM PST 24 Jan 24 09:06:53 PM PST 24 3146034689 ps
T558 /workspace/coverage/default/160.otp_ctrl_init_fail.1594510493 Jan 24 09:53:26 PM PST 24 Jan 24 09:53:31 PM PST 24 370728155 ps
T559 /workspace/coverage/default/156.otp_ctrl_init_fail.3428805593 Jan 24 09:12:50 PM PST 24 Jan 24 09:12:58 PM PST 24 1990074267 ps
T560 /workspace/coverage/default/75.otp_ctrl_init_fail.1672350022 Jan 24 09:08:58 PM PST 24 Jan 24 09:09:04 PM PST 24 2454929179 ps
T76 /workspace/coverage/default/176.otp_ctrl_init_fail.1174376450 Jan 24 11:40:49 PM PST 24 Jan 24 11:40:54 PM PST 24 215492143 ps
T224 /workspace/coverage/default/28.otp_ctrl_regwen.1126899178 Jan 24 09:00:25 PM PST 24 Jan 24 09:00:39 PM PST 24 1101029974 ps
T561 /workspace/coverage/default/180.otp_ctrl_init_fail.2366645762 Jan 24 09:13:42 PM PST 24 Jan 24 09:13:47 PM PST 24 126297552 ps
T251 /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.1397228518 Jan 24 09:11:00 PM PST 24 Jan 24 09:11:11 PM PST 24 3786463348 ps
T262 /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.2954101314 Jan 24 09:09:14 PM PST 24 Jan 24 09:09:20 PM PST 24 2235041379 ps
T562 /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.2583217091 Jan 24 08:55:32 PM PST 24 Jan 24 08:55:36 PM PST 24 177846939 ps
T43 /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.864859446 Jan 24 09:14:29 PM PST 24 Jan 24 09:14:42 PM PST 24 452453520 ps
T563 /workspace/coverage/default/22.otp_ctrl_regwen.1714029776 Jan 24 08:59:12 PM PST 24 Jan 24 08:59:18 PM PST 24 538538784 ps
T564 /workspace/coverage/default/31.otp_ctrl_smoke.2276994568 Jan 24 09:01:07 PM PST 24 Jan 24 09:01:17 PM PST 24 577873243 ps
T565 /workspace/coverage/default/9.otp_ctrl_smoke.1115931701 Jan 24 08:56:05 PM PST 24 Jan 24 08:56:11 PM PST 24 446561591 ps
T566 /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.3166822266 Jan 24 08:57:35 PM PST 24 Jan 24 08:57:45 PM PST 24 442382275 ps
T567 /workspace/coverage/default/80.otp_ctrl_init_fail.1871263217 Jan 24 09:09:42 PM PST 24 Jan 24 09:09:48 PM PST 24 230830036 ps
T568 /workspace/coverage/default/188.otp_ctrl_init_fail.3204298148 Jan 24 09:14:06 PM PST 24 Jan 24 09:14:11 PM PST 24 406352750 ps
T569 /workspace/coverage/default/49.otp_ctrl_alert_test.1611586511 Jan 24 10:51:27 PM PST 24 Jan 24 10:51:31 PM PST 24 121390723 ps
T170 /workspace/coverage/default/133.otp_ctrl_init_fail.3537671477 Jan 24 09:11:53 PM PST 24 Jan 24 09:11:59 PM PST 24 2358395854 ps
T570 /workspace/coverage/default/115.otp_ctrl_init_fail.375733206 Jan 24 09:11:15 PM PST 24 Jan 24 09:11:20 PM PST 24 610327022 ps
T233 /workspace/coverage/default/32.otp_ctrl_smoke.2359951884 Jan 24 09:01:23 PM PST 24 Jan 24 09:01:41 PM PST 24 6460018046 ps
T571 /workspace/coverage/default/38.otp_ctrl_alert_test.1677755759 Jan 24 09:03:15 PM PST 24 Jan 24 09:03:18 PM PST 24 63355433 ps
T572 /workspace/coverage/default/83.otp_ctrl_init_fail.358005634 Jan 24 09:09:40 PM PST 24 Jan 24 09:09:45 PM PST 24 127519957 ps
T573 /workspace/coverage/default/24.otp_ctrl_init_fail.371323358 Jan 24 08:59:32 PM PST 24 Jan 24 08:59:37 PM PST 24 311975732 ps
T574 /workspace/coverage/default/5.otp_ctrl_smoke.1566760566 Jan 24 09:08:25 PM PST 24 Jan 24 09:08:31 PM PST 24 316398034 ps
T199 /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.1929990926 Jan 24 09:09:40 PM PST 24 Jan 24 09:09:46 PM PST 24 266562357 ps
T575 /workspace/coverage/default/14.otp_ctrl_smoke.2397283622 Jan 24 09:16:55 PM PST 24 Jan 24 09:17:01 PM PST 24 545278848 ps
T576 /workspace/coverage/default/74.otp_ctrl_init_fail.729445690 Jan 24 09:08:56 PM PST 24 Jan 24 09:09:02 PM PST 24 2947591581 ps
T577 /workspace/coverage/default/130.otp_ctrl_init_fail.1907882382 Jan 24 09:11:51 PM PST 24 Jan 24 09:11:56 PM PST 24 389141793 ps
T578 /workspace/coverage/default/26.otp_ctrl_smoke.4261757094 Jan 24 09:00:00 PM PST 24 Jan 24 09:00:06 PM PST 24 433014341 ps
T579 /workspace/coverage/default/21.otp_ctrl_alert_test.3205160105 Jan 24 08:59:03 PM PST 24 Jan 24 08:59:06 PM PST 24 111675688 ps
T171 /workspace/coverage/default/134.otp_ctrl_init_fail.2496433908 Jan 24 09:11:54 PM PST 24 Jan 24 09:11:59 PM PST 24 514389059 ps
T274 /workspace/coverage/default/72.otp_ctrl_init_fail.3746831779 Jan 25 12:18:52 AM PST 24 Jan 25 12:18:58 AM PST 24 2420636109 ps
T580 /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.2108710344 Jan 24 09:07:12 PM PST 24 Jan 24 09:07:18 PM PST 24 166800633 ps
T581 /workspace/coverage/default/108.otp_ctrl_init_fail.3717003259 Jan 24 09:43:54 PM PST 24 Jan 24 09:43:59 PM PST 24 271061011 ps
T582 /workspace/coverage/default/286.otp_ctrl_init_fail.2105251369 Jan 24 09:16:21 PM PST 24 Jan 24 09:16:29 PM PST 24 288368964 ps
T583 /workspace/coverage/default/10.otp_ctrl_init_fail.3885159956 Jan 24 09:03:07 PM PST 24 Jan 24 09:03:12 PM PST 24 157504362 ps
T584 /workspace/coverage/default/208.otp_ctrl_init_fail.613425841 Jan 24 09:15:42 PM PST 24 Jan 24 09:15:47 PM PST 24 97040341 ps
T264 /workspace/coverage/default/48.otp_ctrl_init_fail.2442660572 Jan 24 09:07:11 PM PST 24 Jan 24 09:07:17 PM PST 24 711339354 ps
T585 /workspace/coverage/default/276.otp_ctrl_init_fail.3234704931 Jan 24 09:18:52 PM PST 24 Jan 24 09:18:59 PM PST 24 268917624 ps
T586 /workspace/coverage/default/95.otp_ctrl_init_fail.3690217791 Jan 24 09:10:38 PM PST 24 Jan 24 09:10:47 PM PST 24 123097662 ps
T587 /workspace/coverage/default/47.otp_ctrl_regwen.38973620 Jan 24 09:06:48 PM PST 24 Jan 24 09:06:58 PM PST 24 291593488 ps
T588 /workspace/coverage/default/17.otp_ctrl_regwen.2432461833 Jan 24 08:57:51 PM PST 24 Jan 24 08:58:03 PM PST 24 1052321544 ps
T589 /workspace/coverage/default/50.otp_ctrl_init_fail.820810374 Jan 24 09:07:48 PM PST 24 Jan 24 09:07:55 PM PST 24 2014141428 ps
T590 /workspace/coverage/default/219.otp_ctrl_init_fail.1724109980 Jan 24 09:15:36 PM PST 24 Jan 24 09:15:41 PM PST 24 138416260 ps
T172 /workspace/coverage/default/77.otp_ctrl_init_fail.815225596 Jan 24 11:23:19 PM PST 24 Jan 24 11:23:26 PM PST 24 314551144 ps
T591 /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.1213780768 Jan 24 09:10:28 PM PST 24 Jan 24 09:10:34 PM PST 24 134012396 ps
T592 /workspace/coverage/default/0.otp_ctrl_alert_test.1241537012 Jan 24 09:14:44 PM PST 24 Jan 24 09:14:47 PM PST 24 85005543 ps
T593 /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.1098375831 Jan 24 08:59:33 PM PST 24 Jan 24 08:59:38 PM PST 24 108706466 ps
T594 /workspace/coverage/default/34.otp_ctrl_init_fail.577373812 Jan 24 09:01:48 PM PST 24 Jan 24 09:01:55 PM PST 24 544359386 ps
T595 /workspace/coverage/default/46.otp_ctrl_smoke.1541082066 Jan 24 10:05:17 PM PST 24 Jan 24 10:05:23 PM PST 24 363113655 ps
T596 /workspace/coverage/default/91.otp_ctrl_init_fail.4148310468 Jan 24 09:10:34 PM PST 24 Jan 24 09:10:47 PM PST 24 163599967 ps
T597 /workspace/coverage/default/210.otp_ctrl_init_fail.2216656393 Jan 24 09:15:38 PM PST 24 Jan 24 09:15:43 PM PST 24 130511503 ps
T598 /workspace/coverage/default/253.otp_ctrl_init_fail.3403335375 Jan 25 12:03:51 AM PST 24 Jan 25 12:03:55 AM PST 24 397002823 ps
T144 /workspace/coverage/default/0.otp_ctrl_low_freq_read.3378125111 Jan 24 09:49:40 PM PST 24 Jan 24 09:50:02 PM PST 24 7864338630 ps
T599 /workspace/coverage/default/13.otp_ctrl_alert_test.3533954716 Jan 24 08:57:06 PM PST 24 Jan 24 08:57:11 PM PST 24 804540061 ps
T600 /workspace/coverage/default/45.otp_ctrl_alert_test.3324423567 Jan 24 09:04:30 PM PST 24 Jan 24 09:04:33 PM PST 24 60080697 ps
T601 /workspace/coverage/default/26.otp_ctrl_alert_test.1574348295 Jan 24 09:00:07 PM PST 24 Jan 24 09:00:10 PM PST 24 183814187 ps
T602 /workspace/coverage/default/232.otp_ctrl_init_fail.2467553436 Jan 24 09:15:41 PM PST 24 Jan 24 09:15:47 PM PST 24 119816203 ps
T153 /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.930977046 Jan 24 09:12:43 PM PST 24 Jan 24 09:12:47 PM PST 24 116462087 ps
T603 /workspace/coverage/default/168.otp_ctrl_init_fail.1949494993 Jan 24 09:13:42 PM PST 24 Jan 24 09:13:47 PM PST 24 2284510096 ps
T604 /workspace/coverage/default/10.otp_ctrl_regwen.3561795067 Jan 24 08:56:41 PM PST 24 Jan 24 08:56:54 PM PST 24 4273865427 ps
T605 /workspace/coverage/default/43.otp_ctrl_smoke.3653352771 Jan 24 09:03:58 PM PST 24 Jan 24 09:04:11 PM PST 24 130011945 ps
T237 /workspace/coverage/default/45.otp_ctrl_smoke.228407803 Jan 24 09:04:32 PM PST 24 Jan 24 09:04:43 PM PST 24 472820280 ps
T606 /workspace/coverage/default/63.otp_ctrl_init_fail.3240498036 Jan 24 09:08:35 PM PST 24 Jan 24 09:08:40 PM PST 24 275395375 ps
T607 /workspace/coverage/default/189.otp_ctrl_init_fail.2205316687 Jan 24 09:14:03 PM PST 24 Jan 24 09:14:07 PM PST 24 148420869 ps
T608 /workspace/coverage/default/46.otp_ctrl_alert_test.1565339405 Jan 24 09:06:50 PM PST 24 Jan 24 09:06:53 PM PST 24 99871060 ps
T42 /workspace/coverage/default/280.otp_ctrl_init_fail.49813253 Jan 24 09:16:05 PM PST 24 Jan 24 09:16:18 PM PST 24 153541121 ps
T609 /workspace/coverage/default/3.otp_ctrl_init_fail.801700623 Jan 24 08:54:04 PM PST 24 Jan 24 08:54:10 PM PST 24 211416692 ps
T610 /workspace/coverage/default/153.otp_ctrl_init_fail.2927894055 Jan 24 09:12:38 PM PST 24 Jan 24 09:12:43 PM PST 24 447380147 ps
T611 /workspace/coverage/default/35.otp_ctrl_alert_test.2569832896 Jan 24 09:02:07 PM PST 24 Jan 24 09:02:09 PM PST 24 97892340 ps
T612 /workspace/coverage/default/194.otp_ctrl_init_fail.3351803820 Jan 24 09:14:28 PM PST 24 Jan 24 09:14:33 PM PST 24 154576877 ps
T613 /workspace/coverage/default/29.otp_ctrl_smoke.3347963930 Jan 24 09:00:26 PM PST 24 Jan 24 09:00:32 PM PST 24 2299720170 ps
T614 /workspace/coverage/default/1.otp_ctrl_init_fail.3431813707 Jan 24 08:53:28 PM PST 24 Jan 24 08:53:33 PM PST 24 548609795 ps
T615 /workspace/coverage/default/207.otp_ctrl_init_fail.878734662 Jan 24 09:14:50 PM PST 24 Jan 24 09:15:00 PM PST 24 2583882928 ps
T616 /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.2287722493 Jan 24 09:14:07 PM PST 24 Jan 24 09:14:14 PM PST 24 212730536 ps
T617 /workspace/coverage/default/89.otp_ctrl_init_fail.1263084355 Jan 24 09:10:36 PM PST 24 Jan 24 09:10:50 PM PST 24 2581734953 ps
T618 /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.490661791 Jan 24 09:12:08 PM PST 24 Jan 24 09:12:13 PM PST 24 1909430096 ps
T323 /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.2140449159 Jan 24 09:56:04 PM PST 24 Jan 24 09:56:11 PM PST 24 223980595 ps
T619 /workspace/coverage/default/9.otp_ctrl_alert_test.3612295128 Jan 24 08:56:20 PM PST 24 Jan 24 08:56:23 PM PST 24 668931729 ps
T620 /workspace/coverage/default/126.otp_ctrl_init_fail.3796643888 Jan 24 09:11:50 PM PST 24 Jan 24 09:11:54 PM PST 24 159683194 ps
T149 /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.3443545690 Jan 24 09:40:26 PM PST 24 Jan 24 09:40:29 PM PST 24 212002378 ps
T621 /workspace/coverage/default/25.otp_ctrl_alert_test.1726439505 Jan 24 09:00:05 PM PST 24 Jan 24 09:00:08 PM PST 24 78263740 ps
T622 /workspace/coverage/default/1.otp_ctrl_alert_test.3506029592 Jan 24 08:53:59 PM PST 24 Jan 24 08:54:03 PM PST 24 77672970 ps
T623 /workspace/coverage/default/111.otp_ctrl_init_fail.1250607397 Jan 25 12:39:19 AM PST 24 Jan 25 12:39:25 AM PST 24 2557002817 ps
T154 /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.2754966907 Jan 24 09:12:50 PM PST 24 Jan 24 09:12:57 PM PST 24 330970530 ps
T173 /workspace/coverage/default/16.otp_ctrl_init_fail.2088629432 Jan 24 08:57:53 PM PST 24 Jan 24 08:58:02 PM PST 24 496495482 ps
T624 /workspace/coverage/default/267.otp_ctrl_init_fail.1342533859 Jan 24 10:26:56 PM PST 24 Jan 24 10:27:01 PM PST 24 160435279 ps
T241 /workspace/coverage/default/240.otp_ctrl_init_fail.1608403490 Jan 24 09:15:39 PM PST 24 Jan 24 09:15:45 PM PST 24 768625277 ps
T625 /workspace/coverage/default/55.otp_ctrl_init_fail.82307861 Jan 24 09:08:18 PM PST 24 Jan 24 09:08:27 PM PST 24 2073740512 ps
T626 /workspace/coverage/default/48.otp_ctrl_alert_test.2713878226 Jan 24 09:07:14 PM PST 24 Jan 24 09:07:17 PM PST 24 871092330 ps
T627 /workspace/coverage/default/169.otp_ctrl_init_fail.3890724763 Jan 24 09:13:41 PM PST 24 Jan 24 09:13:47 PM PST 24 227079816 ps
T628 /workspace/coverage/default/285.otp_ctrl_init_fail.1255055466 Jan 24 09:16:18 PM PST 24 Jan 24 09:16:31 PM PST 24 1771797270 ps
T16 /workspace/coverage/default/0.otp_ctrl_sec_cm.377363284 Jan 24 08:53:24 PM PST 24 Jan 24 08:57:16 PM PST 24 131373509793 ps
T629 /workspace/coverage/default/41.otp_ctrl_smoke.2470736495 Jan 24 09:03:21 PM PST 24 Jan 24 09:03:25 PM PST 24 384123191 ps
T630 /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.4246636544 Jan 24 09:03:16 PM PST 24 Jan 24 09:03:31 PM PST 24 1830834942 ps
T631 /workspace/coverage/default/182.otp_ctrl_init_fail.1179603418 Jan 24 09:14:08 PM PST 24 Jan 24 09:14:14 PM PST 24 264000148 ps
T310 /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.2618277582 Jan 24 09:08:19 PM PST 24 Jan 24 09:08:27 PM PST 24 223687756 ps
T252 /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.558042015 Jan 24 09:12:05 PM PST 24 Jan 24 09:12:09 PM PST 24 156037380 ps
T632 /workspace/coverage/default/209.otp_ctrl_init_fail.3658396909 Jan 24 09:15:40 PM PST 24 Jan 24 09:15:47 PM PST 24 2057519096 ps
T633 /workspace/coverage/default/45.otp_ctrl_regwen.2467660698 Jan 24 09:04:40 PM PST 24 Jan 24 09:04:46 PM PST 24 442997297 ps
T77 /workspace/coverage/default/123.otp_ctrl_init_fail.2224482435 Jan 24 09:11:50 PM PST 24 Jan 24 09:11:57 PM PST 24 2447993856 ps
T634 /workspace/coverage/default/22.otp_ctrl_alert_test.2141288975 Jan 24 08:59:14 PM PST 24 Jan 24 08:59:17 PM PST 24 181616236 ps
T635 /workspace/coverage/default/298.otp_ctrl_init_fail.3486805797 Jan 24 09:16:36 PM PST 24 Jan 24 09:16:41 PM PST 24 235120690 ps
T636 /workspace/coverage/default/101.otp_ctrl_init_fail.1181803953 Jan 24 09:52:05 PM PST 24 Jan 24 09:52:10 PM PST 24 222765274 ps
T637 /workspace/coverage/default/14.otp_ctrl_alert_test.827002747 Jan 24 08:57:40 PM PST 24 Jan 24 08:57:44 PM PST 24 785440707 ps
T638 /workspace/coverage/default/64.otp_ctrl_init_fail.827070332 Jan 24 09:08:37 PM PST 24 Jan 24 09:08:42 PM PST 24 105029635 ps
T639 /workspace/coverage/default/149.otp_ctrl_init_fail.2703925978 Jan 24 09:12:24 PM PST 24 Jan 24 09:12:30 PM PST 24 297588801 ps
T640 /workspace/coverage/default/10.otp_ctrl_smoke.1027819686 Jan 24 08:56:18 PM PST 24 Jan 24 08:56:27 PM PST 24 453033078 ps
T641 /workspace/coverage/default/35.otp_ctrl_regwen.2612637620 Jan 24 09:02:10 PM PST 24 Jan 24 09:02:20 PM PST 24 3946879506 ps
T642 /workspace/coverage/default/175.otp_ctrl_init_fail.731883547 Jan 24 09:13:47 PM PST 24 Jan 24 09:13:52 PM PST 24 294295793 ps
T200 /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.2498898504 Jan 24 09:13:06 PM PST 24 Jan 24 09:13:15 PM PST 24 118789429 ps
T643 /workspace/coverage/default/200.otp_ctrl_init_fail.2795602160 Jan 24 09:14:53 PM PST 24 Jan 24 09:14:57 PM PST 24 431841137 ps
T644 /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.997805976 Jan 24 09:13:45 PM PST 24 Jan 24 09:13:54 PM PST 24 1801152492 ps
T325 /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.1158400604 Jan 24 09:11:00 PM PST 24 Jan 24 09:11:08 PM PST 24 652500385 ps
T645 /workspace/coverage/default/249.otp_ctrl_init_fail.1505067411 Jan 24 10:02:59 PM PST 24 Jan 24 10:03:04 PM PST 24 159451950 ps
T646 /workspace/coverage/default/28.otp_ctrl_smoke.2884416570 Jan 24 09:00:42 PM PST 24 Jan 24 09:00:50 PM PST 24 3396774783 ps
T217 /workspace/coverage/default/15.otp_ctrl_regwen.912614519 Jan 24 08:57:38 PM PST 24 Jan 24 08:57:50 PM PST 24 320683736 ps
T647 /workspace/coverage/default/17.otp_ctrl_alert_test.4226929861 Jan 24 08:58:07 PM PST 24 Jan 24 08:58:15 PM PST 24 141760431 ps
T648 /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.4215998311 Jan 24 09:32:59 PM PST 24 Jan 24 09:33:05 PM PST 24 245380564 ps
T649 /workspace/coverage/default/37.otp_ctrl_init_fail.989583941 Jan 24 09:02:58 PM PST 24 Jan 24 09:03:04 PM PST 24 2615012872 ps
T650 /workspace/coverage/default/223.otp_ctrl_init_fail.3348043144 Jan 24 09:15:41 PM PST 24 Jan 24 09:15:49 PM PST 24 2720844167 ps
T651 /workspace/coverage/default/231.otp_ctrl_init_fail.1657020963 Jan 24 09:39:32 PM PST 24 Jan 24 09:39:36 PM PST 24 129554360 ps
T652 /workspace/coverage/default/218.otp_ctrl_init_fail.84090383 Jan 24 09:15:38 PM PST 24 Jan 24 09:15:44 PM PST 24 2676906498 ps
T653 /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.2861515410 Jan 24 08:55:18 PM PST 24 Jan 24 08:55:26 PM PST 24 503718157 ps
T267 /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.2675124149 Jan 24 10:20:44 PM PST 24 Jan 24 10:20:54 PM PST 24 480089361 ps
T654 /workspace/coverage/default/82.otp_ctrl_init_fail.3066542914 Jan 24 09:09:39 PM PST 24 Jan 24 09:09:43 PM PST 24 112449978 ps
T232 /workspace/coverage/default/30.otp_ctrl_smoke.1613975812 Jan 24 09:00:53 PM PST 24 Jan 24 09:01:08 PM PST 24 1154138369 ps
T174 /workspace/coverage/default/8.otp_ctrl_init_fail.3114980954 Jan 24 08:55:36 PM PST 24 Jan 24 08:55:42 PM PST 24 628742791 ps
T655 /workspace/coverage/default/120.otp_ctrl_init_fail.1886155365 Jan 24 09:11:28 PM PST 24 Jan 24 09:11:33 PM PST 24 459092974 ps
T656 /workspace/coverage/default/23.otp_ctrl_alert_test.3223463836 Jan 24 08:59:31 PM PST 24 Jan 24 08:59:37 PM PST 24 840648271 ps
T208 /workspace/coverage/default/4.otp_ctrl_smoke.1376895996 Jan 24 09:07:11 PM PST 24 Jan 24 09:07:22 PM PST 24 1731614117 ps
T657 /workspace/coverage/default/48.otp_ctrl_smoke.2060924609 Jan 24 09:07:07 PM PST 24 Jan 24 09:07:14 PM PST 24 874281684 ps
T658 /workspace/coverage/default/23.otp_ctrl_regwen.1093882086 Jan 24 08:59:32 PM PST 24 Jan 24 08:59:35 PM PST 24 265868730 ps
T659 /workspace/coverage/default/6.otp_ctrl_init_fail.4010669249 Jan 24 08:55:17 PM PST 24 Jan 24 08:55:21 PM PST 24 408559153 ps
T660 /workspace/coverage/default/275.otp_ctrl_init_fail.986109522 Jan 24 09:45:28 PM PST 24 Jan 24 09:45:33 PM PST 24 157121975 ps
T661 /workspace/coverage/default/181.otp_ctrl_init_fail.3285717236 Jan 24 09:33:17 PM PST 24 Jan 24 09:33:23 PM PST 24 1869502876 ps
T662 /workspace/coverage/default/31.otp_ctrl_init_fail.1404792568 Jan 24 09:01:06 PM PST 24 Jan 24 09:01:15 PM PST 24 520036243 ps
T663 /workspace/coverage/default/31.otp_ctrl_alert_test.98521705 Jan 24 09:01:27 PM PST 24 Jan 24 09:01:30 PM PST 24 94280868 ps
T242 /workspace/coverage/default/2.otp_ctrl_sec_cm.1839883692 Jan 24 08:54:02 PM PST 24 Jan 24 08:56:42 PM PST 24 18107636890 ps
T664 /workspace/coverage/default/52.otp_ctrl_init_fail.2441085924 Jan 24 09:07:52 PM PST 24 Jan 24 09:07:56 PM PST 24 401748061 ps
T665 /workspace/coverage/default/145.otp_ctrl_init_fail.804820447 Jan 24 09:18:04 PM PST 24 Jan 24 09:18:09 PM PST 24 210932168 ps
T666 /workspace/coverage/default/102.otp_ctrl_init_fail.3120774365 Jan 24 09:10:59 PM PST 24 Jan 24 09:11:05 PM PST 24 106537988 ps
T667 /workspace/coverage/default/235.otp_ctrl_init_fail.1982963251 Jan 24 09:15:36 PM PST 24 Jan 24 09:15:41 PM PST 24 2041237696 ps
T243 /workspace/coverage/default/4.otp_ctrl_sec_cm.3676007973 Jan 24 09:24:11 PM PST 24 Jan 24 09:26:50 PM PST 24 17207051777 ps
T668 /workspace/coverage/default/112.otp_ctrl_init_fail.4229561797 Jan 24 11:10:21 PM PST 24 Jan 24 11:10:26 PM PST 24 141070768 ps
T669 /workspace/coverage/default/23.otp_ctrl_smoke.2476163102 Jan 24 08:59:12 PM PST 24 Jan 24 08:59:24 PM PST 24 4238545480 ps
T235 /workspace/coverage/default/33.otp_ctrl_regwen.3392379136 Jan 24 10:09:16 PM PST 24 Jan 24 10:09:21 PM PST 24 152407278 ps
T670 /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.1347582148 Jan 24 08:59:16 PM PST 24 Jan 24 08:59:22 PM PST 24 356527857 ps
T671 /workspace/coverage/default/272.otp_ctrl_init_fail.579549920 Jan 24 09:16:05 PM PST 24 Jan 24 09:16:19 PM PST 24 1662356146 ps
T672 /workspace/coverage/default/38.otp_ctrl_init_fail.1621626459 Jan 24 09:02:57 PM PST 24 Jan 24 09:03:03 PM PST 24 470714511 ps
T673 /workspace/coverage/default/69.otp_ctrl_init_fail.483197374 Jan 24 09:53:26 PM PST 24 Jan 24 09:53:31 PM PST 24 184900866 ps
T674 /workspace/coverage/default/78.otp_ctrl_init_fail.3826976100 Jan 24 09:44:41 PM PST 24 Jan 24 09:44:46 PM PST 24 139436099 ps
T675 /workspace/coverage/default/41.otp_ctrl_alert_test.2119105427 Jan 24 09:03:19 PM PST 24 Jan 24 09:03:23 PM PST 24 136210043 ps
T676 /workspace/coverage/default/105.otp_ctrl_init_fail.4272917578 Jan 24 09:10:55 PM PST 24 Jan 24 09:11:00 PM PST 24 200373890 ps
T677 /workspace/coverage/default/12.otp_ctrl_init_fail.1830559847 Jan 24 08:58:12 PM PST 24 Jan 24 08:58:20 PM PST 24 124306041 ps
T678 /workspace/coverage/default/23.otp_ctrl_init_fail.2951784781 Jan 24 08:59:09 PM PST 24 Jan 24 08:59:15 PM PST 24 308280647 ps
T679 /workspace/coverage/default/256.otp_ctrl_init_fail.772680830 Jan 24 09:18:51 PM PST 24 Jan 24 09:18:57 PM PST 24 1354195534 ps
T680 /workspace/coverage/default/257.otp_ctrl_init_fail.1085001366 Jan 25 12:13:06 AM PST 24 Jan 25 12:13:12 AM PST 24 142658927 ps
T681 /workspace/coverage/default/229.otp_ctrl_init_fail.682156465 Jan 24 09:15:08 PM PST 24 Jan 24 09:15:13 PM PST 24 290638383 ps
T327 /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.4082185947 Jan 24 10:24:25 PM PST 24 Jan 24 10:24:29 PM PST 24 386313208 ps
T682 /workspace/coverage/default/8.otp_ctrl_alert_test.562445251 Jan 24 08:56:06 PM PST 24 Jan 24 08:56:09 PM PST 24 601545324 ps
T683 /workspace/coverage/default/258.otp_ctrl_init_fail.716966860 Jan 24 09:16:02 PM PST 24 Jan 24 09:16:06 PM PST 24 1787047926 ps
T209 /workspace/coverage/default/26.otp_ctrl_regwen.1586584801 Jan 24 09:20:22 PM PST 24 Jan 24 09:20:32 PM PST 24 1058792294 ps
T684 /workspace/coverage/default/59.otp_ctrl_init_fail.3546767201 Jan 24 09:08:19 PM PST 24 Jan 24 09:08:26 PM PST 24 1974799286 ps
T685 /workspace/coverage/default/56.otp_ctrl_init_fail.2437345117 Jan 24 09:08:19 PM PST 24 Jan 24 09:08:26 PM PST 24 387834606 ps
T686 /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.1670705464 Jan 24 09:44:27 PM PST 24 Jan 24 09:44:37 PM PST 24 619289843 ps
T687 /workspace/coverage/default/44.otp_ctrl_smoke.849544544 Jan 24 09:04:15 PM PST 24 Jan 24 09:04:29 PM PST 24 331466703 ps
T201 /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.3174332467 Jan 24 09:09:13 PM PST 24 Jan 24 09:09:24 PM PST 24 1608841039 ps
T688 /workspace/coverage/default/292.otp_ctrl_init_fail.1572184449 Jan 24 09:16:37 PM PST 24 Jan 24 09:16:41 PM PST 24 144405794 ps
T273 /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.1702226020 Jan 24 10:13:19 PM PST 24 Jan 24 10:13:36 PM PST 24 690027813 ps
T689 /workspace/coverage/default/199.otp_ctrl_init_fail.3326402881 Jan 24 10:34:42 PM PST 24 Jan 24 10:34:53 PM PST 24 129906040 ps
T690 /workspace/coverage/default/186.otp_ctrl_init_fail.87098040 Jan 24 09:14:08 PM PST 24 Jan 24 09:14:13 PM PST 24 192136053 ps
T691 /workspace/coverage/default/190.otp_ctrl_init_fail.936114053 Jan 24 09:14:21 PM PST 24 Jan 24 09:14:25 PM PST 24 120492200 ps
T692 /workspace/coverage/default/260.otp_ctrl_init_fail.1346237589 Jan 24 09:16:03 PM PST 24 Jan 24 09:16:10 PM PST 24 300459805 ps
T693 /workspace/coverage/default/155.otp_ctrl_init_fail.188895919 Jan 24 09:12:38 PM PST 24 Jan 24 09:12:45 PM PST 24 2104337227 ps
T253 /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.2247131008 Jan 24 09:08:43 PM PST 24 Jan 24 09:09:03 PM PST 24 1439525678 ps
T694 /workspace/coverage/default/143.otp_ctrl_init_fail.723777624 Jan 24 09:12:12 PM PST 24 Jan 24 09:12:17 PM PST 24 591676309 ps
T695 /workspace/coverage/default/224.otp_ctrl_init_fail.1940289207 Jan 24 09:15:36 PM PST 24 Jan 24 09:15:40 PM PST 24 458037734 ps
T696 /workspace/coverage/default/281.otp_ctrl_init_fail.2971148524 Jan 24 09:16:17 PM PST 24 Jan 24 09:16:28 PM PST 24 254488410 ps
T697 /workspace/coverage/default/117.otp_ctrl_init_fail.3988220689 Jan 24 09:11:24 PM PST 24 Jan 24 09:11:31 PM PST 24 2672460003 ps
T698 /workspace/coverage/default/217.otp_ctrl_init_fail.1072073227 Jan 24 09:15:39 PM PST 24 Jan 24 09:15:44 PM PST 24 265375329 ps
T699 /workspace/coverage/default/109.otp_ctrl_init_fail.2133711283 Jan 24 09:11:01 PM PST 24 Jan 24 09:11:08 PM PST 24 1473752701 ps
T219 /workspace/coverage/default/27.otp_ctrl_regwen.2499590878 Jan 24 09:00:16 PM PST 24 Jan 24 09:00:24 PM PST 24 3815287359 ps
T700 /workspace/coverage/default/127.otp_ctrl_init_fail.2100352241 Jan 24 09:11:50 PM PST 24 Jan 24 09:11:55 PM PST 24 180579031 ps
T701 /workspace/coverage/default/124.otp_ctrl_init_fail.3833932046 Jan 24 09:11:49 PM PST 24 Jan 24 09:11:53 PM PST 24 453254568 ps
T702 /workspace/coverage/default/284.otp_ctrl_init_fail.3983902018 Jan 24 09:16:20 PM PST 24 Jan 24 09:16:30 PM PST 24 184411840 ps
T703 /workspace/coverage/default/255.otp_ctrl_init_fail.2305152240 Jan 24 09:16:03 PM PST 24 Jan 24 09:16:10 PM PST 24 209988738 ps
T704 /workspace/coverage/default/29.otp_ctrl_regwen.4244634708 Jan 24 09:00:38 PM PST 24 Jan 24 09:00:45 PM PST 24 2109707771 ps
T158 /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.1704387889 Jan 24 09:10:31 PM PST 24 Jan 24 09:10:48 PM PST 24 605790223 ps
T705 /workspace/coverage/default/4.otp_ctrl_init_fail.201795919 Jan 24 08:54:16 PM PST 24 Jan 24 08:54:21 PM PST 24 183420566 ps
T706 /workspace/coverage/default/19.otp_ctrl_smoke.3118362688 Jan 24 08:58:16 PM PST 24 Jan 24 08:58:24 PM PST 24 2359501356 ps
T175 /workspace/coverage/default/113.otp_ctrl_init_fail.1002152161 Jan 24 10:13:17 PM PST 24 Jan 24 10:13:23 PM PST 24 128518763 ps
T707 /workspace/coverage/default/204.otp_ctrl_init_fail.2891655566 Jan 24 09:14:53 PM PST 24 Jan 24 09:14:58 PM PST 24 474538503 ps
T708 /workspace/coverage/default/7.otp_ctrl_regwen.1409064881 Jan 24 08:55:34 PM PST 24 Jan 24 08:55:44 PM PST 24 1095440522 ps
T709 /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.1378232757 Jan 24 09:12:05 PM PST 24 Jan 24 09:12:23 PM PST 24 2264256822 ps
T710 /workspace/coverage/default/14.otp_ctrl_regwen.2273056644 Jan 24 08:57:16 PM PST 24 Jan 24 08:57:24 PM PST 24 758384864 ps
T711 /workspace/coverage/default/36.otp_ctrl_smoke.2553569257 Jan 24 09:02:10 PM PST 24 Jan 24 09:02:20 PM PST 24 283134035 ps
T712 /workspace/coverage/default/103.otp_ctrl_init_fail.123600846 Jan 24 09:10:57 PM PST 24 Jan 24 09:11:03 PM PST 24 712714865 ps
T713 /workspace/coverage/default/220.otp_ctrl_init_fail.2275200313 Jan 24 09:15:41 PM PST 24 Jan 24 09:15:47 PM PST 24 205688918 ps
T714 /workspace/coverage/default/93.otp_ctrl_init_fail.3807486079 Jan 24 09:10:33 PM PST 24 Jan 24 09:10:44 PM PST 24 550318829 ps
T715 /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.3548351832 Jan 24 09:11:00 PM PST 24 Jan 24 09:11:09 PM PST 24 219547256 ps
T716 /workspace/coverage/default/154.otp_ctrl_init_fail.2673296388 Jan 24 09:12:50 PM PST 24 Jan 24 09:12:56 PM PST 24 152328479 ps
T717 /workspace/coverage/default/44.otp_ctrl_init_fail.1361150699 Jan 24 09:12:47 PM PST 24 Jan 24 09:12:52 PM PST 24 657458225 ps
T176 /workspace/coverage/default/45.otp_ctrl_init_fail.114712549 Jan 24 09:33:57 PM PST 24 Jan 24 09:34:03 PM PST 24 344912356 ps
T718 /workspace/coverage/default/20.otp_ctrl_smoke.1204031638 Jan 24 08:58:28 PM PST 24 Jan 24 08:58:38 PM PST 24 1171696861 ps
T719 /workspace/coverage/default/293.otp_ctrl_init_fail.1012421580 Jan 24 09:16:35 PM PST 24 Jan 24 09:16:41 PM PST 24 1870695005 ps
T720 /workspace/coverage/default/30.otp_ctrl_regwen.3635999069 Jan 24 09:00:48 PM PST 24 Jan 24 09:00:55 PM PST 24 167589822 ps
T721 /workspace/coverage/default/27.otp_ctrl_alert_test.1798805464 Jan 24 09:00:26 PM PST 24 Jan 24 09:00:30 PM PST 24 108627841 ps
T722 /workspace/coverage/default/28.otp_ctrl_init_fail.448514998 Jan 24 09:00:26 PM PST 24 Jan 24 09:00:32 PM PST 24 474913056 ps

Test location /workspace/coverage/default/38.otp_ctrl_regwen.1025418246
Short name T5
Test name
Test status
Simulation time 411064771 ps
CPU time 7.19 seconds
Started Jan 24 09:12:45 PM PST 24
Finished Jan 24 09:12:53 PM PST 24
Peak memory 247624 kb
Host smart-392d00c3-f5af-4119-aaa1-a50f55ef7ac8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1025418246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.1025418246
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.24621113
Short name T10
Test name
Test status
Simulation time 1975817182552 ps
CPU time 2795.7 seconds
Started Jan 24 09:09:44 PM PST 24
Finished Jan 24 09:56:21 PM PST 24
Peak memory 258984 kb
Host smart-b853f4b2-8635-4d2f-a3d4-7b7dac13c48c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24621113 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.24621113
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.3109080636
Short name T21
Test name
Test status
Simulation time 2107427513 ps
CPU time 16.32 seconds
Started Jan 24 09:09:45 PM PST 24
Finished Jan 24 09:10:03 PM PST 24
Peak memory 239520 kb
Host smart-1e5bb2c9-a55c-461b-a149-a522046d60ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109080636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.3109080636
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.122396708
Short name T17
Test name
Test status
Simulation time 194622313 ps
CPU time 4.57 seconds
Started Jan 24 09:13:46 PM PST 24
Finished Jan 24 09:13:52 PM PST 24
Peak memory 244084 kb
Host smart-61c1c3fc-b566-4159-a1e1-7695e4036abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122396708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.122396708
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.4148917747
Short name T96
Test name
Test status
Simulation time 2552143493 ps
CPU time 18.13 seconds
Started Jan 24 05:01:18 PM PST 24
Finished Jan 24 05:01:40 PM PST 24
Peak memory 241636 kb
Host smart-1e9e295c-c25c-46d3-952f-f5e04d7a728d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148917747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.4148917747
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.1221417388
Short name T72
Test name
Test status
Simulation time 561779055 ps
CPU time 8.64 seconds
Started Jan 24 08:54:18 PM PST 24
Finished Jan 24 08:54:27 PM PST 24
Peak memory 239620 kb
Host smart-15d364f6-da62-4ca2-8389-086d7281c633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1221417388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.1221417388
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.1330872471
Short name T14
Test name
Test status
Simulation time 21243317248 ps
CPU time 158.09 seconds
Started Jan 24 08:54:16 PM PST 24
Finished Jan 24 08:56:56 PM PST 24
Peak memory 260672 kb
Host smart-709b214e-3b07-4b54-928d-7af45e848a3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330872471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.1330872471
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.2624389565
Short name T32
Test name
Test status
Simulation time 183367759 ps
CPU time 4.67 seconds
Started Jan 24 09:11:00 PM PST 24
Finished Jan 24 09:11:08 PM PST 24
Peak memory 246684 kb
Host smart-cf4dfdec-e2e8-43a7-b735-610a59e21e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624389565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.2624389565
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.4240562976
Short name T52
Test name
Test status
Simulation time 353013840 ps
CPU time 3.78 seconds
Started Jan 24 09:08:20 PM PST 24
Finished Jan 24 09:08:26 PM PST 24
Peak memory 243332 kb
Host smart-62002aad-19ff-45e1-b69d-6c13d30178b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240562976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.4240562976
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.3902344412
Short name T150
Test name
Test status
Simulation time 556982902 ps
CPU time 3.71 seconds
Started Jan 24 08:55:40 PM PST 24
Finished Jan 24 08:55:47 PM PST 24
Peak memory 245556 kb
Host smart-26fe9a9b-8fbe-4bbc-9be6-4b872da98526
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3902344412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.3902344412
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.4016114278
Short name T48
Test name
Test status
Simulation time 518392401 ps
CPU time 5.46 seconds
Started Jan 24 09:12:12 PM PST 24
Finished Jan 24 09:12:18 PM PST 24
Peak memory 244276 kb
Host smart-2599e0d1-aa49-4b8e-af0e-ce6c67381ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016114278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.4016114278
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.1416268394
Short name T35
Test name
Test status
Simulation time 102207385 ps
CPU time 3.98 seconds
Started Jan 24 09:10:27 PM PST 24
Finished Jan 24 09:10:36 PM PST 24
Peak memory 243568 kb
Host smart-1a5d6f08-d613-47ac-97e6-36e159ffecdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416268394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.1416268394
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.3134650838
Short name T19
Test name
Test status
Simulation time 2342267719 ps
CPU time 5.24 seconds
Started Jan 24 09:10:33 PM PST 24
Finished Jan 24 09:10:47 PM PST 24
Peak memory 239600 kb
Host smart-1f302c19-910b-4135-8f01-442d3bb704f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134650838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.3134650838
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.4294611498
Short name T40
Test name
Test status
Simulation time 417720024 ps
CPU time 4.63 seconds
Started Jan 24 08:59:48 PM PST 24
Finished Jan 24 08:59:53 PM PST 24
Peak memory 243804 kb
Host smart-b7d3ddbe-72ac-46fd-9836-fc722bdc18b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294611498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.4294611498
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.257550307
Short name T83
Test name
Test status
Simulation time 337885339 ps
CPU time 4.14 seconds
Started Jan 24 10:52:17 PM PST 24
Finished Jan 24 10:52:25 PM PST 24
Peak memory 239512 kb
Host smart-2b0b84d1-84a8-452a-8f39-0a22cccf4f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257550307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.257550307
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.3717868065
Short name T87
Test name
Test status
Simulation time 535688131 ps
CPU time 4.77 seconds
Started Jan 24 09:02:09 PM PST 24
Finished Jan 24 09:02:17 PM PST 24
Peak memory 246668 kb
Host smart-f1a6decd-ee8c-4106-9987-4bd113f002c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717868065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.3717868065
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.2019247584
Short name T18
Test name
Test status
Simulation time 2601513725 ps
CPU time 4.82 seconds
Started Jan 24 08:58:49 PM PST 24
Finished Jan 24 08:58:58 PM PST 24
Peak memory 239608 kb
Host smart-346ed787-e1a3-41bc-b2ee-d0a17173d52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019247584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.2019247584
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.802494154
Short name T49
Test name
Test status
Simulation time 246975226 ps
CPU time 3.58 seconds
Started Jan 24 09:02:14 PM PST 24
Finished Jan 24 09:02:19 PM PST 24
Peak memory 243924 kb
Host smart-2a6a4296-04e6-4b10-91f8-16695442d051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802494154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.802494154
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.591597181
Short name T1
Test name
Test status
Simulation time 305689095 ps
CPU time 4.28 seconds
Started Jan 24 09:11:25 PM PST 24
Finished Jan 24 09:11:30 PM PST 24
Peak memory 244408 kb
Host smart-6939dd06-8703-4f2c-ad9c-9682ed347cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591597181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.591597181
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.3122509536
Short name T71
Test name
Test status
Simulation time 471612093 ps
CPU time 5.95 seconds
Started Jan 24 09:07:09 PM PST 24
Finished Jan 24 09:07:17 PM PST 24
Peak memory 239640 kb
Host smart-8013fb72-f997-422b-8a04-44a46f7081b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3122509536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.3122509536
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.3688647133
Short name T47
Test name
Test status
Simulation time 186850779 ps
CPU time 3.32 seconds
Started Jan 24 09:18:09 PM PST 24
Finished Jan 24 09:18:15 PM PST 24
Peak memory 243460 kb
Host smart-4c5210a2-df25-47a7-8ced-33159b030e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688647133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.3688647133
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.2410621198
Short name T11
Test name
Test status
Simulation time 147529923 ps
CPU time 2.39 seconds
Started Jan 24 08:58:41 PM PST 24
Finished Jan 24 08:58:45 PM PST 24
Peak memory 239728 kb
Host smart-68388e7d-cea3-43d8-8cea-5cff95311c88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410621198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.2410621198
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.1628073960
Short name T27
Test name
Test status
Simulation time 135160955 ps
CPU time 4 seconds
Started Jan 24 09:55:05 PM PST 24
Finished Jan 24 09:55:21 PM PST 24
Peak memory 243064 kb
Host smart-8238dd8f-66e1-40d3-94d4-222865742224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628073960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.1628073960
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.1312597098
Short name T160
Test name
Test status
Simulation time 509356781 ps
CPU time 8.32 seconds
Started Jan 24 09:10:38 PM PST 24
Finished Jan 24 09:10:51 PM PST 24
Peak memory 245732 kb
Host smart-6900bb00-4b7e-4c88-b7b4-5b66ce7a0955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312597098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.1312597098
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.238945391
Short name T148
Test name
Test status
Simulation time 195586770 ps
CPU time 5.12 seconds
Started Jan 24 09:10:57 PM PST 24
Finished Jan 24 09:11:04 PM PST 24
Peak memory 239568 kb
Host smart-aedc58b9-40f1-42ed-97ee-0ae16fce75d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238945391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.238945391
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.930977046
Short name T153
Test name
Test status
Simulation time 116462087 ps
CPU time 3.13 seconds
Started Jan 24 09:12:43 PM PST 24
Finished Jan 24 09:12:47 PM PST 24
Peak memory 239504 kb
Host smart-42785db0-dd35-42d2-84a2-a3edc3a4a7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930977046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.930977046
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1580277604
Short name T288
Test name
Test status
Simulation time 199067713 ps
CPU time 3.96 seconds
Started Jan 24 04:24:58 PM PST 24
Finished Jan 24 04:25:03 PM PST 24
Peak memory 238020 kb
Host smart-17c42787-34c7-4a70-b397-d03726ebe00d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580277604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.1580277604
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.3353834544
Short name T151
Test name
Test status
Simulation time 398182165 ps
CPU time 3.73 seconds
Started Jan 24 09:11:53 PM PST 24
Finished Jan 24 09:11:57 PM PST 24
Peak memory 244440 kb
Host smart-e5b75847-f8a9-498d-90e0-d2b189a82f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353834544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.3353834544
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.1256917118
Short name T181
Test name
Test status
Simulation time 282796080 ps
CPU time 4.3 seconds
Started Jan 24 09:26:59 PM PST 24
Finished Jan 24 09:27:08 PM PST 24
Peak memory 243052 kb
Host smart-b39f21c5-27b5-4a16-8eff-e531e7192c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256917118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.1256917118
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3315437401
Short name T105
Test name
Test status
Simulation time 483098245 ps
CPU time 3.14 seconds
Started Jan 24 04:27:00 PM PST 24
Finished Jan 24 04:27:05 PM PST 24
Peak memory 238080 kb
Host smart-66ffcb1e-616a-414c-927d-9e9a4de6f6e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315437401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.3315437401
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.3238761493
Short name T29
Test name
Test status
Simulation time 299155025 ps
CPU time 8.13 seconds
Started Jan 24 09:03:13 PM PST 24
Finished Jan 24 09:03:22 PM PST 24
Peak memory 247764 kb
Host smart-6a6e3d51-543b-416d-b20f-14ffc08f28ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3238761493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.3238761493
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.1704387889
Short name T158
Test name
Test status
Simulation time 605790223 ps
CPU time 14.52 seconds
Started Jan 24 09:10:31 PM PST 24
Finished Jan 24 09:10:48 PM PST 24
Peak memory 247644 kb
Host smart-fcb215e2-c62a-4ebe-b276-e039a0043ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704387889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.1704387889
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.3372738735
Short name T82
Test name
Test status
Simulation time 1707779408 ps
CPU time 4.03 seconds
Started Jan 24 09:15:36 PM PST 24
Finished Jan 24 09:15:41 PM PST 24
Peak memory 239464 kb
Host smart-b6df7af5-2ed7-40c6-b36c-bfc827728447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372738735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.3372738735
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.639275252
Short name T147
Test name
Test status
Simulation time 354158206 ps
CPU time 5.08 seconds
Started Jan 24 09:09:41 PM PST 24
Finished Jan 24 09:09:47 PM PST 24
Peak memory 244368 kb
Host smart-5f57700d-bc22-4265-aa5e-55494ad27147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639275252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.639275252
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.2499126472
Short name T227
Test name
Test status
Simulation time 834606456 ps
CPU time 8.58 seconds
Started Jan 24 08:57:42 PM PST 24
Finished Jan 24 08:57:55 PM PST 24
Peak memory 239636 kb
Host smart-577a3a70-7a38-46fd-aa3a-e8ca0727a3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499126472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.2499126472
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.2119285366
Short name T45
Test name
Test status
Simulation time 152114699 ps
CPU time 4.36 seconds
Started Jan 24 11:40:52 PM PST 24
Finished Jan 24 11:40:58 PM PST 24
Peak memory 244244 kb
Host smart-b185b960-af61-4f78-9f61-cad319af8d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119285366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.2119285366
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.2250512035
Short name T13
Test name
Test status
Simulation time 1863019951 ps
CPU time 5.18 seconds
Started Jan 24 08:58:19 PM PST 24
Finished Jan 24 08:58:26 PM PST 24
Peak memory 245188 kb
Host smart-4c804d5f-0d5e-4a91-8fda-b1309c0540d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250512035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.2250512035
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.864859446
Short name T43
Test name
Test status
Simulation time 452453520 ps
CPU time 12.11 seconds
Started Jan 24 09:14:29 PM PST 24
Finished Jan 24 09:14:42 PM PST 24
Peak memory 245972 kb
Host smart-be64ef7f-e169-4e66-99bb-03ef894eba67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864859446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.864859446
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.3493467608
Short name T117
Test name
Test status
Simulation time 40388952 ps
CPU time 1.4 seconds
Started Jan 24 04:27:11 PM PST 24
Finished Jan 24 04:27:22 PM PST 24
Peak memory 229868 kb
Host smart-039e32ed-0790-4acf-a8f3-e87e9479c1f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493467608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.3493467608
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.2954101314
Short name T262
Test name
Test status
Simulation time 2235041379 ps
CPU time 5.08 seconds
Started Jan 24 09:09:14 PM PST 24
Finished Jan 24 09:09:20 PM PST 24
Peak memory 244268 kb
Host smart-2c33fd09-a89c-4479-a759-f563e42cbb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954101314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.2954101314
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.1170482023
Short name T80
Test name
Test status
Simulation time 307564158 ps
CPU time 4.13 seconds
Started Jan 24 09:29:20 PM PST 24
Finished Jan 24 09:29:28 PM PST 24
Peak memory 239472 kb
Host smart-559cbcc9-8b0d-4070-9efc-38a8733fcd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170482023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.1170482023
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.299016155
Short name T207
Test name
Test status
Simulation time 508472251 ps
CPU time 8.65 seconds
Started Jan 24 08:58:45 PM PST 24
Finished Jan 24 08:58:58 PM PST 24
Peak memory 239580 kb
Host smart-c52dfb35-742d-4e36-973c-b9d67ce105ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299016155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.299016155
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.558042015
Short name T252
Test name
Test status
Simulation time 156037380 ps
CPU time 3.71 seconds
Started Jan 24 09:12:05 PM PST 24
Finished Jan 24 09:12:09 PM PST 24
Peak memory 239496 kb
Host smart-48ae396e-8879-468e-af89-79a77f73dc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558042015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.558042015
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.3737751846
Short name T543
Test name
Test status
Simulation time 526813131 ps
CPU time 9.64 seconds
Started Jan 24 09:04:12 PM PST 24
Finished Jan 24 09:04:30 PM PST 24
Peak memory 239620 kb
Host smart-7e8a156e-f2f3-4bb8-be6a-ead0fb6f9a38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3737751846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.3737751846
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.2224482435
Short name T77
Test name
Test status
Simulation time 2447993856 ps
CPU time 5.8 seconds
Started Jan 24 09:11:50 PM PST 24
Finished Jan 24 09:11:57 PM PST 24
Peak memory 244104 kb
Host smart-c1fbd1e1-2975-4d5e-9814-dfc233f2ab2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224482435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.2224482435
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.471951012
Short name T190
Test name
Test status
Simulation time 2327315429 ps
CPU time 4.25 seconds
Started Jan 24 09:09:43 PM PST 24
Finished Jan 24 09:09:48 PM PST 24
Peak memory 243900 kb
Host smart-9ebab58b-00ff-4d43-809b-af62630c665c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471951012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.471951012
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.3443545690
Short name T149
Test name
Test status
Simulation time 212002378 ps
CPU time 3.14 seconds
Started Jan 24 09:40:26 PM PST 24
Finished Jan 24 09:40:29 PM PST 24
Peak memory 244588 kb
Host smart-45c93a1c-d546-4323-8267-70df933d52cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443545690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.3443545690
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.2772915824
Short name T216
Test name
Test status
Simulation time 1103794481 ps
CPU time 7.17 seconds
Started Jan 24 08:58:52 PM PST 24
Finished Jan 24 08:59:02 PM PST 24
Peak memory 239628 kb
Host smart-1e680cbc-bc9e-451d-b3c5-879f6d043873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772915824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.2772915824
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.1702226020
Short name T273
Test name
Test status
Simulation time 690027813 ps
CPU time 15.33 seconds
Started Jan 24 10:13:19 PM PST 24
Finished Jan 24 10:13:36 PM PST 24
Peak memory 239564 kb
Host smart-3deb87ee-a903-4c05-90f6-87b1a1f7fe19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702226020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.1702226020
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.2482975776
Short name T548
Test name
Test status
Simulation time 163433517 ps
CPU time 3.88 seconds
Started Jan 24 09:15:38 PM PST 24
Finished Jan 24 09:15:44 PM PST 24
Peak memory 238864 kb
Host smart-2398b497-fb80-452b-99b1-2a64e2f26850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482975776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.2482975776
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.1036169764
Short name T109
Test name
Test status
Simulation time 19464279929 ps
CPU time 35.23 seconds
Started Jan 24 04:25:39 PM PST 24
Finished Jan 24 04:26:30 PM PST 24
Peak memory 242052 kb
Host smart-6828d0e9-3b47-40e3-beda-489e0d9aabc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036169764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.1036169764
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.2922888232
Short name T313
Test name
Test status
Simulation time 451818200 ps
CPU time 7.57 seconds
Started Jan 24 09:01:38 PM PST 24
Finished Jan 24 09:01:47 PM PST 24
Peak memory 238964 kb
Host smart-e7dbe469-7286-40d3-ab2f-8cf31be424ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922888232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.2922888232
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.1158400604
Short name T325
Test name
Test status
Simulation time 652500385 ps
CPU time 4.76 seconds
Started Jan 24 09:11:00 PM PST 24
Finished Jan 24 09:11:08 PM PST 24
Peak memory 239604 kb
Host smart-86fac269-220c-484e-9154-4a3d552a8d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158400604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.1158400604
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.266684077
Short name T66
Test name
Test status
Simulation time 595132046 ps
CPU time 4.36 seconds
Started Jan 24 09:06:50 PM PST 24
Finished Jan 24 09:06:56 PM PST 24
Peak memory 242428 kb
Host smart-5a7124c9-ca6b-4852-a891-967bf04927e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266684077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.266684077
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.2552695830
Short name T319
Test name
Test status
Simulation time 2303626569 ps
CPU time 9.49 seconds
Started Jan 24 04:26:03 PM PST 24
Finished Jan 24 04:26:15 PM PST 24
Peak memory 241428 kb
Host smart-37b8b219-2c3c-4d19-a174-fe6ee124c435
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552695830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.2552695830
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.3578436857
Short name T120
Test name
Test status
Simulation time 70811087 ps
CPU time 1.39 seconds
Started Jan 24 04:27:09 PM PST 24
Finished Jan 24 04:27:17 PM PST 24
Peak memory 229892 kb
Host smart-026e7f42-0c25-4a7a-8ef0-43f15d758feb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578436857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.3578436857
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.2167157180
Short name T152
Test name
Test status
Simulation time 166297450 ps
CPU time 7.49 seconds
Started Jan 24 09:11:54 PM PST 24
Finished Jan 24 09:12:03 PM PST 24
Peak memory 239472 kb
Host smart-5abbb942-a822-48cd-b000-148ea8e2afcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167157180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.2167157180
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.599488092
Short name T256
Test name
Test status
Simulation time 1691864874 ps
CPU time 5.39 seconds
Started Jan 24 09:08:37 PM PST 24
Finished Jan 24 09:08:44 PM PST 24
Peak memory 244984 kb
Host smart-b1ace88f-cd5d-4cd7-a7d6-7322894e6989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599488092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.599488092
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.1929990926
Short name T199
Test name
Test status
Simulation time 266562357 ps
CPU time 4.61 seconds
Started Jan 24 09:09:40 PM PST 24
Finished Jan 24 09:09:46 PM PST 24
Peak memory 239508 kb
Host smart-aeff5438-86a7-4896-9a01-6a40ffcb9b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929990926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.1929990926
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.4059141249
Short name T196
Test name
Test status
Simulation time 1795349965 ps
CPU time 5.48 seconds
Started Jan 24 09:09:41 PM PST 24
Finished Jan 24 09:09:47 PM PST 24
Peak memory 239548 kb
Host smart-bee529d3-559d-481a-af33-21b793df50f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059141249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.4059141249
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.2126157079
Short name T122
Test name
Test status
Simulation time 76274458 ps
CPU time 2.19 seconds
Started Jan 24 04:25:42 PM PST 24
Finished Jan 24 04:25:57 PM PST 24
Peak memory 238096 kb
Host smart-37732bee-9492-4d4e-97e4-c0e75fd31c94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126157079 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.2126157079
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.1437660642
Short name T265
Test name
Test status
Simulation time 130785488 ps
CPU time 4.02 seconds
Started Jan 24 09:07:50 PM PST 24
Finished Jan 24 09:07:57 PM PST 24
Peak memory 244360 kb
Host smart-f3f9f24a-9f91-4cd6-9338-7b26254d23e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437660642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.1437660642
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.123600846
Short name T712
Test name
Test status
Simulation time 712714865 ps
CPU time 5.46 seconds
Started Jan 24 09:10:57 PM PST 24
Finished Jan 24 09:11:03 PM PST 24
Peak memory 239612 kb
Host smart-8a7afd01-f564-46e0-aa0d-1e8002758d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123600846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.123600846
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.2364922931
Short name T221
Test name
Test status
Simulation time 1569231436 ps
CPU time 8.23 seconds
Started Jan 24 08:55:20 PM PST 24
Finished Jan 24 08:55:29 PM PST 24
Peak memory 239668 kb
Host smart-57915ac0-8855-4a30-9d6d-ece1d83e3313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364922931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.2364922931
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.4199506653
Short name T236
Test name
Test status
Simulation time 316953397 ps
CPU time 8.12 seconds
Started Jan 24 08:55:46 PM PST 24
Finished Jan 24 08:55:58 PM PST 24
Peak memory 239676 kb
Host smart-216e8ec5-b90f-470d-81f9-8a4ae984e816
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4199506653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.4199506653
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.398637986
Short name T334
Test name
Test status
Simulation time 537232362 ps
CPU time 4.64 seconds
Started Jan 24 09:01:49 PM PST 24
Finished Jan 24 09:01:57 PM PST 24
Peak memory 243688 kb
Host smart-53550a24-6695-486d-a5fe-f196b4567695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398637986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.398637986
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.3504918160
Short name T51
Test name
Test status
Simulation time 1506595403 ps
CPU time 4.04 seconds
Started Jan 24 08:58:03 PM PST 24
Finished Jan 24 08:58:13 PM PST 24
Peak memory 239532 kb
Host smart-6df18805-4886-4b46-b0ed-44472b7cf93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504918160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.3504918160
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.1608403490
Short name T241
Test name
Test status
Simulation time 768625277 ps
CPU time 4.39 seconds
Started Jan 24 09:15:39 PM PST 24
Finished Jan 24 09:15:45 PM PST 24
Peak memory 247700 kb
Host smart-a22b3551-dd77-4dac-8750-1ca219f0370f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608403490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.1608403490
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.3782161434
Short name T119
Test name
Test status
Simulation time 102499951 ps
CPU time 2.07 seconds
Started Jan 24 04:25:01 PM PST 24
Finished Jan 24 04:25:05 PM PST 24
Peak memory 229812 kb
Host smart-892b7fe8-0021-4ffc-9c39-6056a0aee2d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782161434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r
eset.3782161434
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.3851389955
Short name T246
Test name
Test status
Simulation time 2824560137 ps
CPU time 5.83 seconds
Started Jan 24 09:12:25 PM PST 24
Finished Jan 24 09:12:31 PM PST 24
Peak memory 244200 kb
Host smart-5c288042-e233-491c-943c-edc5cc963adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851389955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.3851389955
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.590601945
Short name T85
Test name
Test status
Simulation time 676884694 ps
CPU time 5.01 seconds
Started Jan 24 09:14:07 PM PST 24
Finished Jan 24 09:14:13 PM PST 24
Peak memory 243424 kb
Host smart-209f3c1f-5755-462c-806d-86df09543fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590601945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.590601945
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.1839883692
Short name T242
Test name
Test status
Simulation time 18107636890 ps
CPU time 158.74 seconds
Started Jan 24 08:54:02 PM PST 24
Finished Jan 24 08:56:42 PM PST 24
Peak memory 269588 kb
Host smart-e370c5c7-2a72-41dd-9a14-0409b7c377a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839883692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.1839883692
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.2884416570
Short name T646
Test name
Test status
Simulation time 3396774783 ps
CPU time 7.36 seconds
Started Jan 24 09:00:42 PM PST 24
Finished Jan 24 09:00:50 PM PST 24
Peak memory 239768 kb
Host smart-ac38036a-3f46-4756-9d23-36157c774b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884416570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.2884416570
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.2437345117
Short name T685
Test name
Test status
Simulation time 387834606 ps
CPU time 4.62 seconds
Started Jan 24 09:08:19 PM PST 24
Finished Jan 24 09:08:26 PM PST 24
Peak memory 242940 kb
Host smart-da3376c4-a77f-4307-84bd-5845e1a75522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437345117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.2437345117
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.2766789265
Short name T212
Test name
Test status
Simulation time 547580841 ps
CPU time 5.46 seconds
Started Jan 24 09:31:15 PM PST 24
Finished Jan 24 09:31:21 PM PST 24
Peak memory 239616 kb
Host smart-91cd7a61-d5ca-468c-9eed-1d440e987b3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2766789265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.2766789265
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.440203685
Short name T348
Test name
Test status
Simulation time 208700860 ps
CPU time 3.63 seconds
Started Jan 24 09:31:11 PM PST 24
Finished Jan 24 09:31:16 PM PST 24
Peak memory 243420 kb
Host smart-bb721329-e884-4f7c-8ed6-9d2b3512d550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440203685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.440203685
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.4229561797
Short name T668
Test name
Test status
Simulation time 141070768 ps
CPU time 4.19 seconds
Started Jan 24 11:10:21 PM PST 24
Finished Jan 24 11:10:26 PM PST 24
Peak memory 239592 kb
Host smart-e2bf2b46-35c1-46b4-8a6f-0abf5c7576d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229561797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.4229561797
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.788187658
Short name T272
Test name
Test status
Simulation time 353934831 ps
CPU time 5.35 seconds
Started Jan 24 09:10:36 PM PST 24
Finished Jan 24 09:10:48 PM PST 24
Peak memory 239484 kb
Host smart-f106988b-bda6-4abf-a6a0-ee2a8b924d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788187658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.788187658
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.1580026466
Short name T86
Test name
Test status
Simulation time 460223951 ps
CPU time 4.16 seconds
Started Jan 24 09:16:58 PM PST 24
Finished Jan 24 09:17:03 PM PST 24
Peak memory 246688 kb
Host smart-ab3d2255-ace2-46a1-953d-c50460f624c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580026466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.1580026466
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.883815844
Short name T23
Test name
Test status
Simulation time 2881400077 ps
CPU time 9.09 seconds
Started Jan 24 09:12:39 PM PST 24
Finished Jan 24 09:12:49 PM PST 24
Peak memory 239728 kb
Host smart-d47d053b-d4c3-40af-8be8-bc8f459c6aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883815844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.883815844
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.2553569257
Short name T711
Test name
Test status
Simulation time 283134035 ps
CPU time 7.64 seconds
Started Jan 24 09:02:10 PM PST 24
Finished Jan 24 09:02:20 PM PST 24
Peak memory 239604 kb
Host smart-ef82358d-284e-4334-a86d-8c1d9b31e42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553569257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.2553569257
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3531385644
Short name T94
Test name
Test status
Simulation time 1604306951 ps
CPU time 4.18 seconds
Started Jan 24 04:26:08 PM PST 24
Finished Jan 24 04:26:14 PM PST 24
Peak memory 245812 kb
Host smart-ef8b3aab-8aa0-4e35-9726-184068cce6f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531385644 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.3531385644
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1633382497
Short name T93
Test name
Test status
Simulation time 4515390638 ps
CPU time 19.37 seconds
Started Jan 24 04:26:40 PM PST 24
Finished Jan 24 04:27:09 PM PST 24
Peak memory 230208 kb
Host smart-987c0d3f-3c55-48ac-a31d-88e93fa9db08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633382497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.1633382497
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.2442660572
Short name T264
Test name
Test status
Simulation time 711339354 ps
CPU time 4.84 seconds
Started Jan 24 09:07:11 PM PST 24
Finished Jan 24 09:07:17 PM PST 24
Peak memory 244156 kb
Host smart-90c8328e-f5c0-4410-a12c-a9f4ea9c4dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442660572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.2442660572
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.2136751807
Short name T215
Test name
Test status
Simulation time 3900761680 ps
CPU time 10.38 seconds
Started Jan 24 08:57:53 PM PST 24
Finished Jan 24 08:58:06 PM PST 24
Peak memory 239688 kb
Host smart-4ab2a59a-f59d-43f5-bbd0-00f299ba7124
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2136751807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.2136751807
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.803576859
Short name T24
Test name
Test status
Simulation time 2441893588 ps
CPU time 6.86 seconds
Started Jan 24 09:11:20 PM PST 24
Finished Jan 24 09:11:28 PM PST 24
Peak memory 244216 kb
Host smart-ba50a794-7f8e-4a4f-a86a-f677b6ded10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803576859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.803576859
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.2318211434
Short name T218
Test name
Test status
Simulation time 285160348 ps
CPU time 4.39 seconds
Started Jan 24 08:56:51 PM PST 24
Finished Jan 24 08:56:57 PM PST 24
Peak memory 239540 kb
Host smart-3a1f44a4-2b4f-4454-844e-4c50d72f78df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318211434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.2318211434
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.2313411904
Short name T146
Test name
Test status
Simulation time 302288699 ps
CPU time 8.33 seconds
Started Jan 24 09:41:31 PM PST 24
Finished Jan 24 09:41:41 PM PST 24
Peak memory 245780 kb
Host smart-4e1ca0a9-b628-4036-980e-888a3dae90e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313411904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.2313411904
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.188478702
Short name T30
Test name
Test status
Simulation time 159486489 ps
CPU time 3.95 seconds
Started Jan 24 09:41:32 PM PST 24
Finished Jan 24 09:41:37 PM PST 24
Peak memory 242620 kb
Host smart-952a189d-1776-494b-b493-0c3fab71c4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188478702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.188478702
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.248826459
Short name T477
Test name
Test status
Simulation time 2490859200 ps
CPU time 3.92 seconds
Started Jan 24 09:15:40 PM PST 24
Finished Jan 24 09:15:47 PM PST 24
Peak memory 239568 kb
Host smart-5786ee93-2193-407e-8fe8-508ab05d3b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248826459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.248826459
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.2743484847
Short name T25
Test name
Test status
Simulation time 632245564 ps
CPU time 4.87 seconds
Started Jan 24 09:11:04 PM PST 24
Finished Jan 24 09:11:11 PM PST 24
Peak memory 245232 kb
Host smart-72606ee0-0d82-4150-b7eb-a2865d5c3639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743484847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.2743484847
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.3830086457
Short name T50
Test name
Test status
Simulation time 202297244 ps
CPU time 4.46 seconds
Started Jan 24 09:12:24 PM PST 24
Finished Jan 24 09:12:30 PM PST 24
Peak memory 243600 kb
Host smart-dbba3b27-f4ec-4e70-9547-2eaad491a0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830086457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.3830086457
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.1102277026
Short name T538
Test name
Test status
Simulation time 228336072 ps
CPU time 3.68 seconds
Started Jan 24 09:13:45 PM PST 24
Finished Jan 24 09:13:50 PM PST 24
Peak memory 244632 kb
Host smart-3c3e1e90-73fb-4c46-8688-8342f84bf67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102277026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.1102277026
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.2130083440
Short name T60
Test name
Test status
Simulation time 260203284 ps
CPU time 3.51 seconds
Started Jan 24 09:14:09 PM PST 24
Finished Jan 24 09:14:15 PM PST 24
Peak memory 244224 kb
Host smart-cf9ba81c-5abd-4bdc-b644-6f1e1d9b6a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130083440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.2130083440
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.1346237589
Short name T692
Test name
Test status
Simulation time 300459805 ps
CPU time 4.89 seconds
Started Jan 24 09:16:03 PM PST 24
Finished Jan 24 09:16:10 PM PST 24
Peak memory 243404 kb
Host smart-aad7e30c-b6e7-419a-8e73-1694473752df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346237589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.1346237589
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.3532026783
Short name T55
Test name
Test status
Simulation time 201358463 ps
CPU time 3.81 seconds
Started Jan 24 09:16:34 PM PST 24
Finished Jan 24 09:16:39 PM PST 24
Peak memory 239472 kb
Host smart-94c365d9-83fa-4689-b79b-c92ad279289b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532026783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.3532026783
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.3340188616
Short name T506
Test name
Test status
Simulation time 503830161 ps
CPU time 3.92 seconds
Started Jan 24 09:56:29 PM PST 24
Finished Jan 24 09:56:34 PM PST 24
Peak memory 239512 kb
Host smart-4d9cd52f-8d70-438b-b265-b956e2ba32a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340188616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.3340188616
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.3044759767
Short name T540
Test name
Test status
Simulation time 583974688 ps
CPU time 4.46 seconds
Started Jan 24 09:13:44 PM PST 24
Finished Jan 24 09:13:50 PM PST 24
Peak memory 243360 kb
Host smart-8deaa883-9239-422f-ac57-efc9156ae12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044759767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.3044759767
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.1204031638
Short name T718
Test name
Test status
Simulation time 1171696861 ps
CPU time 8.58 seconds
Started Jan 24 08:58:28 PM PST 24
Finished Jan 24 08:58:38 PM PST 24
Peak memory 243604 kb
Host smart-790123f2-0c7f-407f-9c04-dadb005d7409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204031638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.1204031638
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.4107522834
Short name T20
Test name
Test status
Simulation time 261470805 ps
CPU time 3.1 seconds
Started Jan 24 09:08:36 PM PST 24
Finished Jan 24 09:08:41 PM PST 24
Peak memory 243288 kb
Host smart-0b88f375-941a-4d84-870b-13d3af117cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107522834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.4107522834
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.3561795067
Short name T604
Test name
Test status
Simulation time 4273865427 ps
CPU time 10.98 seconds
Started Jan 24 08:56:41 PM PST 24
Finished Jan 24 08:56:54 PM PST 24
Peak memory 244408 kb
Host smart-3cbc4481-46f6-414d-b6c0-85156bb60a54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561795067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.3561795067
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.1027819686
Short name T640
Test name
Test status
Simulation time 453033078 ps
CPU time 7.22 seconds
Started Jan 24 08:56:18 PM PST 24
Finished Jan 24 08:56:27 PM PST 24
Peak memory 239688 kb
Host smart-52446333-098d-4362-9651-41c627386004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027819686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.1027819686
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.2675124149
Short name T267
Test name
Test status
Simulation time 480089361 ps
CPU time 9.62 seconds
Started Jan 24 10:20:44 PM PST 24
Finished Jan 24 10:20:54 PM PST 24
Peak memory 245772 kb
Host smart-b1dff14b-ff79-48e8-a88e-8d18c442e9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675124149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.2675124149
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.375733206
Short name T570
Test name
Test status
Simulation time 610327022 ps
CPU time 3.99 seconds
Started Jan 24 09:11:15 PM PST 24
Finished Jan 24 09:11:20 PM PST 24
Peak memory 243244 kb
Host smart-aa1cb2c1-5864-4ead-be60-2f54440653e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375733206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.375733206
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.1083196189
Short name T62
Test name
Test status
Simulation time 150506972 ps
CPU time 4.07 seconds
Started Jan 24 09:11:50 PM PST 24
Finished Jan 24 09:11:55 PM PST 24
Peak memory 243576 kb
Host smart-ceca5053-7b2d-4365-9716-8522abd2a3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083196189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.1083196189
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.613425841
Short name T584
Test name
Test status
Simulation time 97040341 ps
CPU time 3.46 seconds
Started Jan 24 09:15:42 PM PST 24
Finished Jan 24 09:15:47 PM PST 24
Peak memory 242656 kb
Host smart-8fcb89c2-84f3-4879-8d92-9a9f79ba3b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613425841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.613425841
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.1316404165
Short name T504
Test name
Test status
Simulation time 341920104 ps
CPU time 10.07 seconds
Started Jan 24 09:25:58 PM PST 24
Finished Jan 24 09:26:09 PM PST 24
Peak memory 239648 kb
Host smart-e8972624-2354-4e30-85e1-db11f3828377
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1316404165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.1316404165
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.1586584801
Short name T209
Test name
Test status
Simulation time 1058792294 ps
CPU time 10.06 seconds
Started Jan 24 09:20:22 PM PST 24
Finished Jan 24 09:20:32 PM PST 24
Peak memory 239676 kb
Host smart-33592d24-ed67-4672-97ee-1b14c05592e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1586584801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.1586584801
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.307490190
Short name T229
Test name
Test status
Simulation time 359269089 ps
CPU time 6.17 seconds
Started Jan 24 09:07:23 PM PST 24
Finished Jan 24 09:07:31 PM PST 24
Peak memory 239632 kb
Host smart-bc8ffe07-97a6-43c9-96a5-4b869b4a3793
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=307490190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.307490190
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.2499590878
Short name T219
Test name
Test status
Simulation time 3815287359 ps
CPU time 7.56 seconds
Started Jan 24 09:00:16 PM PST 24
Finished Jan 24 09:00:24 PM PST 24
Peak memory 239716 kb
Host smart-c863c3ac-c76b-4bee-9412-44036fd95fa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2499590878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.2499590878
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.3967367415
Short name T7
Test name
Test status
Simulation time 585836763 ps
CPU time 4.27 seconds
Started Jan 24 09:20:05 PM PST 24
Finished Jan 24 09:20:09 PM PST 24
Peak memory 239632 kb
Host smart-88501cdc-46bd-4eee-b9ec-166e1ebb51a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967367415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.3967367415
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1024452523
Short name T408
Test name
Test status
Simulation time 383282712 ps
CPU time 8.51 seconds
Started Jan 24 04:44:38 PM PST 24
Finished Jan 24 04:44:47 PM PST 24
Peak memory 229812 kb
Host smart-327a4e4c-14df-4b92-a4bc-0a15974eb949
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024452523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.1024452523
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2852856379
Short name T394
Test name
Test status
Simulation time 231647379 ps
CPU time 2.32 seconds
Started Jan 24 04:24:55 PM PST 24
Finished Jan 24 04:24:58 PM PST 24
Peak memory 243924 kb
Host smart-482e3180-d739-4b04-9602-44ad698259f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852856379 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.2852856379
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1223590224
Short name T287
Test name
Test status
Simulation time 38564347 ps
CPU time 1.58 seconds
Started Jan 24 04:24:59 PM PST 24
Finished Jan 24 04:25:03 PM PST 24
Peak memory 229780 kb
Host smart-0db02324-ea0d-4317-bfda-d1f9ebaa9539
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223590224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.1223590224
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.3205059823
Short name T138
Test name
Test status
Simulation time 133939128 ps
CPU time 1.29 seconds
Started Jan 24 04:24:51 PM PST 24
Finished Jan 24 04:24:54 PM PST 24
Peak memory 229788 kb
Host smart-b9aec3cd-4ca2-40a8-b235-6ab000e97be5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205059823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.3205059823
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.770727521
Short name T426
Test name
Test status
Simulation time 134581376 ps
CPU time 1.48 seconds
Started Jan 24 04:24:57 PM PST 24
Finished Jan 24 04:25:00 PM PST 24
Peak memory 229552 kb
Host smart-aa819afd-6e2d-473b-ac27-1072feccb93a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770727521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl
_mem_partial_access.770727521
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.868700122
Short name T393
Test name
Test status
Simulation time 128339872 ps
CPU time 1.35 seconds
Started Jan 24 04:25:00 PM PST 24
Finished Jan 24 04:25:03 PM PST 24
Peak memory 229532 kb
Host smart-16cbd1a6-7aff-43d4-82d2-a12d3857b37e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868700122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.
868700122
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.2939594654
Short name T107
Test name
Test status
Simulation time 93063157 ps
CPU time 2.6 seconds
Started Jan 24 04:24:59 PM PST 24
Finished Jan 24 04:25:03 PM PST 24
Peak memory 239040 kb
Host smart-d672674d-e33d-42ae-92a0-3fe8cc8fcb21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939594654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.2939594654
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1380225169
Short name T362
Test name
Test status
Simulation time 249054158 ps
CPU time 5.29 seconds
Started Jan 24 04:37:05 PM PST 24
Finished Jan 24 04:37:12 PM PST 24
Peak memory 243528 kb
Host smart-1418cd03-38f2-4e58-83b0-a980f693346e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380225169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.1380225169
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.817170723
Short name T321
Test name
Test status
Simulation time 736187779 ps
CPU time 10.16 seconds
Started Jan 24 04:24:52 PM PST 24
Finished Jan 24 04:25:04 PM PST 24
Peak memory 240828 kb
Host smart-11f2c414-1197-4ba6-a4c0-6ea4c925475c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817170723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_int
g_err.817170723
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1973231678
Short name T294
Test name
Test status
Simulation time 80902853 ps
CPU time 3.08 seconds
Started Jan 24 04:25:07 PM PST 24
Finished Jan 24 04:25:13 PM PST 24
Peak memory 238056 kb
Host smart-6cf455ec-d00d-40b8-85c2-388b35f794b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973231678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia
sing.1973231678
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1644207917
Short name T139
Test name
Test status
Simulation time 117164516 ps
CPU time 2.23 seconds
Started Jan 24 04:47:12 PM PST 24
Finished Jan 24 04:47:15 PM PST 24
Peak memory 229868 kb
Host smart-9d4009cc-ad0c-4e21-88d3-c7a85efb1ab2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644207917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.1644207917
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3304699857
Short name T386
Test name
Test status
Simulation time 60848064 ps
CPU time 2.26 seconds
Started Jan 24 04:25:08 PM PST 24
Finished Jan 24 04:25:12 PM PST 24
Peak memory 242392 kb
Host smart-d79ca9e2-a9ad-4da9-834f-0cd2b0904bd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304699857 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.3304699857
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3194726503
Short name T420
Test name
Test status
Simulation time 75476747 ps
CPU time 1.57 seconds
Started Jan 24 04:52:35 PM PST 24
Finished Jan 24 04:52:39 PM PST 24
Peak memory 229884 kb
Host smart-ccad1a71-6d5a-42f9-a47c-77efcc007bbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194726503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.3194726503
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.4272339175
Short name T275
Test name
Test status
Simulation time 37570829 ps
CPU time 1.37 seconds
Started Jan 24 04:24:57 PM PST 24
Finished Jan 24 04:24:59 PM PST 24
Peak memory 229812 kb
Host smart-4e174de8-11df-4de2-8daa-3b17e1ac59de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272339175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.4272339175
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2194583012
Short name T135
Test name
Test status
Simulation time 70031231 ps
CPU time 1.39 seconds
Started Jan 24 04:25:06 PM PST 24
Finished Jan 24 04:25:09 PM PST 24
Peak memory 229556 kb
Host smart-f1462b5b-b59d-4a4b-a5a0-03659fc8574d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194583012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.2194583012
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.602350643
Short name T390
Test name
Test status
Simulation time 45655949 ps
CPU time 1.46 seconds
Started Jan 24 04:24:56 PM PST 24
Finished Jan 24 04:24:59 PM PST 24
Peak memory 229532 kb
Host smart-b481c987-de1e-493e-b406-4d25b0327943
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602350643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.
602350643
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.115869534
Short name T365
Test name
Test status
Simulation time 150913636 ps
CPU time 2.84 seconds
Started Jan 24 05:16:41 PM PST 24
Finished Jan 24 05:16:44 PM PST 24
Peak memory 238152 kb
Host smart-4b8ccc25-1a64-4f4f-81eb-886608e09eb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115869534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ct
rl_same_csr_outstanding.115869534
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3512745168
Short name T384
Test name
Test status
Simulation time 383105809 ps
CPU time 4.17 seconds
Started Jan 24 04:25:00 PM PST 24
Finished Jan 24 04:25:06 PM PST 24
Peak memory 238184 kb
Host smart-55cfeac8-7f27-4068-88b6-d7d4bd8ed7ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512745168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.3512745168
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.4239461533
Short name T127
Test name
Test status
Simulation time 1178319921 ps
CPU time 9.9 seconds
Started Jan 24 04:24:59 PM PST 24
Finished Jan 24 04:25:11 PM PST 24
Peak memory 241028 kb
Host smart-e7114683-8289-473e-8111-39cc88c27736
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239461533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.4239461533
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3760945659
Short name T286
Test name
Test status
Simulation time 41167072 ps
CPU time 1.47 seconds
Started Jan 24 04:26:04 PM PST 24
Finished Jan 24 04:26:08 PM PST 24
Peak memory 229856 kb
Host smart-113842e3-aa86-446c-86f5-99e40ed3453c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760945659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.3760945659
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.617749061
Short name T381
Test name
Test status
Simulation time 124820986 ps
CPU time 1.35 seconds
Started Jan 24 04:26:04 PM PST 24
Finished Jan 24 04:26:08 PM PST 24
Peak memory 229784 kb
Host smart-8c84048a-5a65-4653-9a5a-c022942ecdd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617749061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.617749061
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.506473122
Short name T124
Test name
Test status
Simulation time 1010166316 ps
CPU time 2.05 seconds
Started Jan 24 04:26:09 PM PST 24
Finished Jan 24 04:26:12 PM PST 24
Peak memory 238124 kb
Host smart-fe1b6ae8-cc9a-46b5-a238-3400d41b1fcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506473122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_c
trl_same_csr_outstanding.506473122
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.4056793739
Short name T277
Test name
Test status
Simulation time 589480703 ps
CPU time 5.15 seconds
Started Jan 24 04:26:05 PM PST 24
Finished Jan 24 04:26:12 PM PST 24
Peak memory 238064 kb
Host smart-abdc9b2d-91d2-4a21-b8d3-864f3249fd76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056793739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.4056793739
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.3614745921
Short name T320
Test name
Test status
Simulation time 2379142728 ps
CPU time 11.38 seconds
Started Jan 24 04:26:08 PM PST 24
Finished Jan 24 04:26:21 PM PST 24
Peak memory 241204 kb
Host smart-4912ffc8-1b2f-46f5-ab67-f8ecf15894f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614745921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.3614745921
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3873918597
Short name T328
Test name
Test status
Simulation time 253169081 ps
CPU time 3.77 seconds
Started Jan 24 05:12:07 PM PST 24
Finished Jan 24 05:12:11 PM PST 24
Peak memory 238164 kb
Host smart-92b3f429-d8c0-4d92-950e-a10b0318125f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873918597 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.3873918597
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.2750579499
Short name T304
Test name
Test status
Simulation time 129118324 ps
CPU time 1.47 seconds
Started Jan 24 04:26:14 PM PST 24
Finished Jan 24 04:26:17 PM PST 24
Peak memory 229876 kb
Host smart-5a6292df-f6e6-4f82-a2f7-5ac5d6f86550
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750579499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.2750579499
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.777759616
Short name T364
Test name
Test status
Simulation time 83366757 ps
CPU time 1.3 seconds
Started Jan 24 04:26:07 PM PST 24
Finished Jan 24 04:26:09 PM PST 24
Peak memory 229808 kb
Host smart-0e2bd2cf-5ff7-426f-b979-17e38333ed12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777759616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.777759616
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1328741840
Short name T417
Test name
Test status
Simulation time 231369959 ps
CPU time 1.97 seconds
Started Jan 24 04:26:15 PM PST 24
Finished Jan 24 04:26:17 PM PST 24
Peak memory 229948 kb
Host smart-5e3d311b-40a7-49c1-a0f1-47ca05f8eb84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328741840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.1328741840
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.1339415410
Short name T142
Test name
Test status
Simulation time 243983064 ps
CPU time 5.35 seconds
Started Jan 24 04:26:03 PM PST 24
Finished Jan 24 04:26:11 PM PST 24
Peak memory 238144 kb
Host smart-6e549878-9d01-45ed-8aa9-1cdf5722a63b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339415410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.1339415410
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1739743330
Short name T423
Test name
Test status
Simulation time 107798358 ps
CPU time 2.81 seconds
Started Jan 24 04:26:28 PM PST 24
Finished Jan 24 04:26:39 PM PST 24
Peak memory 238152 kb
Host smart-06b0e351-f4ed-4415-8344-e5b7689d1700
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739743330 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.1739743330
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.2535418889
Short name T289
Test name
Test status
Simulation time 41644226 ps
CPU time 1.55 seconds
Started Jan 24 04:45:58 PM PST 24
Finished Jan 24 04:46:01 PM PST 24
Peak memory 229772 kb
Host smart-9323c64d-fe56-4576-b7ff-1a21ef2dd00c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535418889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.2535418889
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.4281406111
Short name T377
Test name
Test status
Simulation time 75970690 ps
CPU time 1.37 seconds
Started Jan 24 04:26:14 PM PST 24
Finished Jan 24 04:26:16 PM PST 24
Peak memory 229880 kb
Host smart-8bfb7fcb-a93f-4bc3-bb6c-3031e0e6676e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281406111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.4281406111
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2321684602
Short name T290
Test name
Test status
Simulation time 79687460 ps
CPU time 2.58 seconds
Started Jan 24 04:26:23 PM PST 24
Finished Jan 24 04:26:28 PM PST 24
Peak memory 238104 kb
Host smart-01a2e299-6f58-4e46-ab5f-05bcf513c6ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321684602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.2321684602
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.1210929039
Short name T300
Test name
Test status
Simulation time 337525293 ps
CPU time 5.61 seconds
Started Jan 24 04:26:12 PM PST 24
Finished Jan 24 04:26:19 PM PST 24
Peak memory 244400 kb
Host smart-abdbeef5-0e8d-4686-ab58-0c47086615aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210929039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.1210929039
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.901228518
Short name T397
Test name
Test status
Simulation time 87047077 ps
CPU time 3.18 seconds
Started Jan 24 04:26:25 PM PST 24
Finished Jan 24 04:26:31 PM PST 24
Peak memory 238156 kb
Host smart-50e04d5d-9ed7-4921-a682-96ac1d564e0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901228518 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.901228518
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.2758676821
Short name T284
Test name
Test status
Simulation time 143636153 ps
CPU time 1.51 seconds
Started Jan 24 04:26:26 PM PST 24
Finished Jan 24 04:26:30 PM PST 24
Peak memory 229828 kb
Host smart-25f8ddb3-12e7-4808-ab5e-8c9be3339ebe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758676821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.2758676821
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2135358777
Short name T434
Test name
Test status
Simulation time 91538963 ps
CPU time 1.48 seconds
Started Jan 24 04:32:52 PM PST 24
Finished Jan 24 04:32:54 PM PST 24
Peak memory 229892 kb
Host smart-9280d425-37d8-474b-b02a-fcde9d02bb21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135358777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.2135358777
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.221208750
Short name T305
Test name
Test status
Simulation time 229723476 ps
CPU time 3.19 seconds
Started Jan 24 04:26:28 PM PST 24
Finished Jan 24 04:26:39 PM PST 24
Peak memory 238112 kb
Host smart-87cf64a6-5ab9-499f-b69d-25c7ef4e855c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221208750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_c
trl_same_csr_outstanding.221208750
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1401794950
Short name T91
Test name
Test status
Simulation time 4937203750 ps
CPU time 18.11 seconds
Started Jan 24 04:26:27 PM PST 24
Finished Jan 24 04:26:51 PM PST 24
Peak memory 230152 kb
Host smart-2a1c5f9c-e943-4f3c-9e77-65997fbf5757
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401794950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.1401794950
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.495366391
Short name T206
Test name
Test status
Simulation time 71485738 ps
CPU time 1.57 seconds
Started Jan 24 04:39:19 PM PST 24
Finished Jan 24 04:39:24 PM PST 24
Peak memory 229852 kb
Host smart-327cc5e8-886e-4458-b510-8c7a51beec49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495366391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.495366391
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.1203437596
Short name T419
Test name
Test status
Simulation time 80829657 ps
CPU time 1.33 seconds
Started Jan 24 04:43:36 PM PST 24
Finished Jan 24 04:43:38 PM PST 24
Peak memory 229872 kb
Host smart-03014e2d-bb56-4698-8c82-8b57290d926f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203437596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.1203437596
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1551125615
Short name T128
Test name
Test status
Simulation time 127752022 ps
CPU time 1.92 seconds
Started Jan 24 04:26:33 PM PST 24
Finished Jan 24 04:26:43 PM PST 24
Peak memory 238024 kb
Host smart-70006c91-1dbb-44f6-945b-4869c4ff14ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551125615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.1551125615
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.4011828192
Short name T89
Test name
Test status
Simulation time 330522492 ps
CPU time 6.01 seconds
Started Jan 24 04:26:28 PM PST 24
Finished Jan 24 04:26:42 PM PST 24
Peak memory 238144 kb
Host smart-72fa5404-f127-4a8d-a404-71d2bf2648f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011828192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.4011828192
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2926098678
Short name T412
Test name
Test status
Simulation time 3657788609 ps
CPU time 20.03 seconds
Started Jan 24 04:26:35 PM PST 24
Finished Jan 24 04:27:02 PM PST 24
Peak memory 241932 kb
Host smart-8a5b42fb-6417-4127-9433-f402902ae027
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926098678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.2926098678
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.2446934845
Short name T329
Test name
Test status
Simulation time 352873232 ps
CPU time 3.46 seconds
Started Jan 24 04:53:07 PM PST 24
Finished Jan 24 04:53:12 PM PST 24
Peak memory 245800 kb
Host smart-e3b4d0c5-d681-4098-b0f9-31e2a80631f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446934845 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.2446934845
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3526391959
Short name T293
Test name
Test status
Simulation time 618057906 ps
CPU time 1.72 seconds
Started Jan 24 04:26:34 PM PST 24
Finished Jan 24 04:26:43 PM PST 24
Peak memory 229844 kb
Host smart-7d94e4e6-a0a1-487f-a14d-959f0f849ea9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526391959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.3526391959
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.307187984
Short name T392
Test name
Test status
Simulation time 73736985 ps
CPU time 1.48 seconds
Started Jan 24 04:26:35 PM PST 24
Finished Jan 24 04:26:43 PM PST 24
Peak memory 229864 kb
Host smart-a57af144-c76c-4eb3-8efe-d0fa0e43876a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307187984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.307187984
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.376137197
Short name T276
Test name
Test status
Simulation time 52179814 ps
CPU time 2.93 seconds
Started Jan 24 05:01:54 PM PST 24
Finished Jan 24 05:02:14 PM PST 24
Peak memory 238084 kb
Host smart-a6f81bd1-632b-492a-94c0-edf47b4f24d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376137197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.376137197
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.423359692
Short name T315
Test name
Test status
Simulation time 2356743111 ps
CPU time 12.73 seconds
Started Jan 24 04:26:32 PM PST 24
Finished Jan 24 04:26:54 PM PST 24
Peak memory 238336 kb
Host smart-086fc73e-8606-4bce-b6b4-0a95bf640def
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423359692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_in
tg_err.423359692
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1141274534
Short name T389
Test name
Test status
Simulation time 175573166 ps
CPU time 2.4 seconds
Started Jan 24 04:26:48 PM PST 24
Finished Jan 24 04:26:55 PM PST 24
Peak memory 238092 kb
Host smart-d5d07e8f-2589-4c46-9224-869fd30b3f56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141274534 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.1141274534
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.2595302345
Short name T283
Test name
Test status
Simulation time 115231526 ps
CPU time 1.5 seconds
Started Jan 24 04:26:49 PM PST 24
Finished Jan 24 04:26:55 PM PST 24
Peak memory 229856 kb
Host smart-fe796a44-695b-496a-ab97-eb5fb87c9a08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595302345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.2595302345
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.694156637
Short name T116
Test name
Test status
Simulation time 86292486 ps
CPU time 1.37 seconds
Started Jan 24 04:26:50 PM PST 24
Finished Jan 24 04:26:56 PM PST 24
Peak memory 229868 kb
Host smart-322506d5-bbc2-4f74-b06e-07778a8f05b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694156637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.694156637
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.227073403
Short name T108
Test name
Test status
Simulation time 2025001081 ps
CPU time 5.23 seconds
Started Jan 24 04:26:48 PM PST 24
Finished Jan 24 04:26:58 PM PST 24
Peak memory 238964 kb
Host smart-c42cab29-3f4b-48f6-b30e-8b2cf648f090
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227073403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_c
trl_same_csr_outstanding.227073403
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1970749900
Short name T92
Test name
Test status
Simulation time 78317787 ps
CPU time 5.37 seconds
Started Jan 24 04:26:41 PM PST 24
Finished Jan 24 04:26:55 PM PST 24
Peak memory 238044 kb
Host smart-541ed7ca-c7ae-4b18-9c16-af61b5221dc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970749900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.1970749900
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.574156460
Short name T97
Test name
Test status
Simulation time 100537610 ps
CPU time 3.45 seconds
Started Jan 24 04:26:48 PM PST 24
Finished Jan 24 04:26:56 PM PST 24
Peak memory 246368 kb
Host smart-205c3e78-08a7-4f84-ba5f-ef7671667f88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574156460 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.574156460
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.39423227
Short name T115
Test name
Test status
Simulation time 58058762 ps
CPU time 1.53 seconds
Started Jan 24 04:26:50 PM PST 24
Finished Jan 24 04:26:56 PM PST 24
Peak memory 229760 kb
Host smart-07252a16-f161-42bd-a0ba-7b88646de2ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39423227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.39423227
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.820508358
Short name T414
Test name
Test status
Simulation time 129572773 ps
CPU time 1.32 seconds
Started Jan 24 04:26:48 PM PST 24
Finished Jan 24 04:26:54 PM PST 24
Peak memory 229844 kb
Host smart-cb41f588-2825-4ce7-9aea-2fb716e37bd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820508358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.820508358
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.191323097
Short name T402
Test name
Test status
Simulation time 45416632 ps
CPU time 1.79 seconds
Started Jan 24 04:26:50 PM PST 24
Finished Jan 24 04:26:57 PM PST 24
Peak memory 238980 kb
Host smart-f7744d2e-ce1a-4f31-81d0-73f0ce5aff57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191323097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_c
trl_same_csr_outstanding.191323097
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1074952917
Short name T430
Test name
Test status
Simulation time 325504298 ps
CPU time 3.43 seconds
Started Jan 24 04:26:52 PM PST 24
Finished Jan 24 04:26:59 PM PST 24
Peak memory 238176 kb
Host smart-47db6394-87de-4fde-a39c-afab0386a73d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074952917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1074952917
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.834062595
Short name T95
Test name
Test status
Simulation time 1244672796 ps
CPU time 10.74 seconds
Started Jan 24 04:26:50 PM PST 24
Finished Jan 24 04:27:05 PM PST 24
Peak memory 240940 kb
Host smart-800c0f29-b434-4735-986a-5dbd3f4e41b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834062595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_in
tg_err.834062595
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1232401732
Short name T376
Test name
Test status
Simulation time 139416429 ps
CPU time 2.38 seconds
Started Jan 24 04:26:59 PM PST 24
Finished Jan 24 04:27:04 PM PST 24
Peak memory 238092 kb
Host smart-e7d391d3-1a2e-477c-86bc-e422885786d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232401732 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.1232401732
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.740056757
Short name T112
Test name
Test status
Simulation time 47917802 ps
CPU time 1.43 seconds
Started Jan 24 04:26:53 PM PST 24
Finished Jan 24 04:26:57 PM PST 24
Peak memory 229856 kb
Host smart-a983bbdc-3ff9-4ccd-88ca-120a6f00b3f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740056757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.740056757
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.141041039
Short name T391
Test name
Test status
Simulation time 543168640 ps
CPU time 1.97 seconds
Started Jan 24 04:26:49 PM PST 24
Finished Jan 24 04:26:56 PM PST 24
Peak memory 229868 kb
Host smart-13c1ede0-0ac0-4310-869c-c4ad7e33040c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141041039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.141041039
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2289315218
Short name T131
Test name
Test status
Simulation time 231351046 ps
CPU time 3.59 seconds
Started Jan 24 04:26:53 PM PST 24
Finished Jan 24 04:26:59 PM PST 24
Peak memory 238156 kb
Host smart-b093a5ee-2d93-4e22-a306-de86bd07bdd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289315218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.2289315218
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3545707471
Short name T140
Test name
Test status
Simulation time 2583099358 ps
CPU time 9.29 seconds
Started Jan 24 04:26:52 PM PST 24
Finished Jan 24 04:27:05 PM PST 24
Peak memory 238320 kb
Host smart-f42d4291-28ff-417c-aa83-f9040a735ea2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545707471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.3545707471
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1767262561
Short name T415
Test name
Test status
Simulation time 123003937 ps
CPU time 3.94 seconds
Started Jan 24 05:54:56 PM PST 24
Finished Jan 24 05:55:01 PM PST 24
Peak memory 238160 kb
Host smart-4a44fa16-41b2-49d0-8e85-f74900a3d251
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767262561 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.1767262561
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.106021035
Short name T296
Test name
Test status
Simulation time 525504554 ps
CPU time 1.52 seconds
Started Jan 24 05:30:56 PM PST 24
Finished Jan 24 05:30:58 PM PST 24
Peak memory 229872 kb
Host smart-4faf6a56-75a5-4f41-a35d-4aed61919d6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106021035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.106021035
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1620594162
Short name T303
Test name
Test status
Simulation time 40652047 ps
CPU time 1.44 seconds
Started Jan 24 04:27:00 PM PST 24
Finished Jan 24 04:27:04 PM PST 24
Peak memory 229872 kb
Host smart-1ed79f2f-4b08-43c0-9435-98c3976347ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620594162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.1620594162
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3498802181
Short name T123
Test name
Test status
Simulation time 958752350 ps
CPU time 2.25 seconds
Started Jan 24 04:27:07 PM PST 24
Finished Jan 24 04:27:10 PM PST 24
Peak memory 238120 kb
Host smart-2ae19958-be88-4af2-b4d5-112a16029335
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498802181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.3498802181
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.596350934
Short name T383
Test name
Test status
Simulation time 177614615 ps
CPU time 4.91 seconds
Started Jan 24 04:27:00 PM PST 24
Finished Jan 24 04:27:07 PM PST 24
Peak memory 238168 kb
Host smart-52ed6409-29a1-483b-bb28-4fee23307ba5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596350934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.596350934
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.3211599110
Short name T422
Test name
Test status
Simulation time 1247060127 ps
CPU time 18.12 seconds
Started Jan 24 04:27:03 PM PST 24
Finished Jan 24 04:27:24 PM PST 24
Peak memory 230036 kb
Host smart-1109ee82-4d6f-4118-883e-4e40a0b08b65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211599110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.3211599110
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.1053314322
Short name T359
Test name
Test status
Simulation time 320644529 ps
CPU time 3.03 seconds
Started Jan 24 04:25:14 PM PST 24
Finished Jan 24 04:25:19 PM PST 24
Peak memory 229792 kb
Host smart-0b28390e-0392-41be-8d7e-f4dfacdb4483
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053314322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.1053314322
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2771837866
Short name T427
Test name
Test status
Simulation time 240977163 ps
CPU time 5.46 seconds
Started Jan 24 04:25:15 PM PST 24
Finished Jan 24 04:25:21 PM PST 24
Peak memory 238012 kb
Host smart-02d2e6f8-d7f6-46da-8ce1-a0129192dc34
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771837866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.2771837866
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2637236864
Short name T285
Test name
Test status
Simulation time 973005522 ps
CPU time 2.07 seconds
Started Jan 24 04:25:14 PM PST 24
Finished Jan 24 04:25:17 PM PST 24
Peak memory 229836 kb
Host smart-339c1f97-d796-401c-97cd-00fd3ca8dda0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637236864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r
eset.2637236864
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.111318549
Short name T387
Test name
Test status
Simulation time 143822338 ps
CPU time 2.29 seconds
Started Jan 24 04:25:28 PM PST 24
Finished Jan 24 04:25:32 PM PST 24
Peak memory 244512 kb
Host smart-7cbc6cd4-9348-40e9-9c16-8f44e81e4385
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111318549 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.111318549
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.735963378
Short name T292
Test name
Test status
Simulation time 44987934 ps
CPU time 1.67 seconds
Started Jan 24 04:25:12 PM PST 24
Finished Jan 24 04:25:15 PM PST 24
Peak memory 229836 kb
Host smart-64673104-08ab-41af-afe8-2fb993dbb0f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735963378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.735963378
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.1222246564
Short name T355
Test name
Test status
Simulation time 532808361 ps
CPU time 1.78 seconds
Started Jan 24 04:25:05 PM PST 24
Finished Jan 24 04:25:08 PM PST 24
Peak memory 229836 kb
Host smart-3218fa3b-d3af-4ef2-8ce6-5ed9f08257a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222246564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.1222246564
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.3248354874
Short name T291
Test name
Test status
Simulation time 140925119 ps
CPU time 1.36 seconds
Started Jan 24 04:25:06 PM PST 24
Finished Jan 24 04:25:09 PM PST 24
Peak memory 229528 kb
Host smart-7a9120b9-4a12-4225-9f1b-11adc833f54b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248354874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.3248354874
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.444881729
Short name T409
Test name
Test status
Simulation time 65842159 ps
CPU time 1.39 seconds
Started Jan 24 04:44:50 PM PST 24
Finished Jan 24 04:44:52 PM PST 24
Peak memory 229524 kb
Host smart-8db9219e-046f-45ea-8f66-10c7e026d2aa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444881729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.
444881729
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3116079813
Short name T368
Test name
Test status
Simulation time 61694838 ps
CPU time 2.19 seconds
Started Jan 24 04:25:13 PM PST 24
Finished Jan 24 04:25:17 PM PST 24
Peak memory 238092 kb
Host smart-e34865e9-8822-418b-ab5e-6c1fec20da14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116079813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.3116079813
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.1452082062
Short name T134
Test name
Test status
Simulation time 2319553531 ps
CPU time 7.47 seconds
Started Jan 24 04:25:06 PM PST 24
Finished Jan 24 04:25:15 PM PST 24
Peak memory 238224 kb
Host smart-e981cc6e-c95b-4013-8a5e-05a58e418e1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452082062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.1452082062
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.891517545
Short name T395
Test name
Test status
Simulation time 139662928 ps
CPU time 1.37 seconds
Started Jan 24 04:27:06 PM PST 24
Finished Jan 24 04:27:09 PM PST 24
Peak memory 229888 kb
Host smart-e1b1f29f-e7dc-486a-a83a-dadabce3b858
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891517545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.891517545
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.4081530291
Short name T404
Test name
Test status
Simulation time 561487549 ps
CPU time 1.98 seconds
Started Jan 24 04:27:00 PM PST 24
Finished Jan 24 04:27:04 PM PST 24
Peak memory 229792 kb
Host smart-ceafd401-2c15-4ce4-93bf-391e8864062e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081530291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.4081530291
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.1037956496
Short name T405
Test name
Test status
Simulation time 41366708 ps
CPU time 1.39 seconds
Started Jan 24 04:26:58 PM PST 24
Finished Jan 24 04:27:01 PM PST 24
Peak memory 229852 kb
Host smart-ff8b5186-3542-4a08-822f-381e2d18cdff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037956496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.1037956496
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.1091607780
Short name T403
Test name
Test status
Simulation time 37467486 ps
CPU time 1.35 seconds
Started Jan 24 06:27:23 PM PST 24
Finished Jan 24 06:27:25 PM PST 24
Peak memory 229828 kb
Host smart-47834144-a051-4946-b12f-64a1c936ae8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091607780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.1091607780
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3725561422
Short name T137
Test name
Test status
Simulation time 129822897 ps
CPU time 1.43 seconds
Started Jan 24 04:27:01 PM PST 24
Finished Jan 24 04:27:05 PM PST 24
Peak memory 229812 kb
Host smart-8b2cf000-a162-463b-bd79-11df31d94e5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725561422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.3725561422
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.3816632080
Short name T401
Test name
Test status
Simulation time 38309974 ps
CPU time 1.41 seconds
Started Jan 24 04:27:00 PM PST 24
Finished Jan 24 04:27:04 PM PST 24
Peak memory 229884 kb
Host smart-7ffd0861-7006-4a42-bd77-67a7dda41a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816632080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.3816632080
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.383581638
Short name T396
Test name
Test status
Simulation time 71963602 ps
CPU time 1.38 seconds
Started Jan 24 04:27:00 PM PST 24
Finished Jan 24 04:27:04 PM PST 24
Peak memory 229880 kb
Host smart-5ffafbdd-9177-41a3-86f8-f7e699f2ea4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383581638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.383581638
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.821178601
Short name T425
Test name
Test status
Simulation time 139800389 ps
CPU time 1.38 seconds
Started Jan 24 05:10:27 PM PST 24
Finished Jan 24 05:10:32 PM PST 24
Peak memory 229864 kb
Host smart-9a2746b6-ab6d-4a58-8b56-59c513eec76e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821178601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.821178601
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.314206072
Short name T407
Test name
Test status
Simulation time 71089512 ps
CPU time 1.43 seconds
Started Jan 24 04:27:13 PM PST 24
Finished Jan 24 04:27:25 PM PST 24
Peak memory 229840 kb
Host smart-796e5024-8769-4dd1-87cf-a38282c0fa8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314206072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.314206072
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2137739598
Short name T371
Test name
Test status
Simulation time 139090117 ps
CPU time 1.38 seconds
Started Jan 24 04:27:09 PM PST 24
Finished Jan 24 04:27:17 PM PST 24
Peak memory 229872 kb
Host smart-b9b40984-4680-4510-baa3-878a84ce32c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137739598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.2137739598
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.847580765
Short name T297
Test name
Test status
Simulation time 2013826880 ps
CPU time 5.03 seconds
Started Jan 24 04:25:31 PM PST 24
Finished Jan 24 04:25:37 PM PST 24
Peak memory 238004 kb
Host smart-033eb164-50c4-49d8-bfec-b29b8dc8af62
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847580765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alias
ing.847580765
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1374394091
Short name T106
Test name
Test status
Simulation time 1905635454 ps
CPU time 11.15 seconds
Started Jan 24 04:25:31 PM PST 24
Finished Jan 24 04:25:44 PM PST 24
Peak memory 229808 kb
Host smart-82997d57-907d-46d4-a7d8-fc1732b7238d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374394091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.1374394091
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3664037634
Short name T433
Test name
Test status
Simulation time 130147189 ps
CPU time 1.84 seconds
Started Jan 24 04:25:31 PM PST 24
Finished Jan 24 04:25:34 PM PST 24
Peak memory 229744 kb
Host smart-5d95d072-096e-4219-9ef7-46dd2cb58e3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664037634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.3664037634
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.3593451251
Short name T125
Test name
Test status
Simulation time 399479394 ps
CPU time 3.35 seconds
Started Jan 24 04:25:34 PM PST 24
Finished Jan 24 04:25:40 PM PST 24
Peak memory 238080 kb
Host smart-3a2cb0a1-9fc6-4a69-b6dd-c545c197987f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593451251 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.3593451251
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.350653521
Short name T111
Test name
Test status
Simulation time 159805675 ps
CPU time 1.84 seconds
Started Jan 24 04:25:27 PM PST 24
Finished Jan 24 04:25:30 PM PST 24
Peak memory 229792 kb
Host smart-d4f4349c-818b-411b-8f68-bb1efab62d2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350653521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.350653521
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.3631564478
Short name T410
Test name
Test status
Simulation time 39013510 ps
CPU time 1.31 seconds
Started Jan 24 04:25:31 PM PST 24
Finished Jan 24 04:25:34 PM PST 24
Peak memory 229808 kb
Host smart-5fb40c51-575d-43b2-914e-b4a08a0e9a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631564478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.3631564478
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.6787297
Short name T399
Test name
Test status
Simulation time 38907875 ps
CPU time 1.33 seconds
Started Jan 24 04:25:31 PM PST 24
Finished Jan 24 04:25:33 PM PST 24
Peak memory 229500 kb
Host smart-118c5d96-f60a-4a7f-b813-6f05a3939b89
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6787297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_m
em_partial_access.6787297
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3740613205
Short name T130
Test name
Test status
Simulation time 65656764 ps
CPU time 1.34 seconds
Started Jan 24 04:25:26 PM PST 24
Finished Jan 24 04:25:28 PM PST 24
Peak memory 229568 kb
Host smart-a9802b7b-3153-45ea-bc4a-675246401722
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740613205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.3740613205
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.38323133
Short name T358
Test name
Test status
Simulation time 43644287 ps
CPU time 1.69 seconds
Started Jan 24 04:25:27 PM PST 24
Finished Jan 24 04:25:29 PM PST 24
Peak memory 238240 kb
Host smart-80b45076-1743-4ac3-b011-f343a613d76f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38323133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_same_csr_outstanding.38323133
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3889737368
Short name T416
Test name
Test status
Simulation time 2244914900 ps
CPU time 6.54 seconds
Started Jan 24 04:25:29 PM PST 24
Finished Jan 24 04:25:37 PM PST 24
Peak memory 238148 kb
Host smart-01e2908b-7424-4ef4-ad86-f72599ec9123
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889737368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.3889737368
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2767430255
Short name T382
Test name
Test status
Simulation time 1519881401 ps
CPU time 9.73 seconds
Started Jan 24 04:25:28 PM PST 24
Finished Jan 24 04:25:39 PM PST 24
Peak memory 229900 kb
Host smart-c2495221-2fa8-4cee-abf0-057056afe52f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767430255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.2767430255
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.1136913137
Short name T428
Test name
Test status
Simulation time 150449294 ps
CPU time 1.57 seconds
Started Jan 24 04:51:35 PM PST 24
Finished Jan 24 04:51:38 PM PST 24
Peak memory 229868 kb
Host smart-c60a69d8-9b5f-4e94-83da-c52584017c58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136913137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.1136913137
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.994170611
Short name T429
Test name
Test status
Simulation time 563347625 ps
CPU time 1.4 seconds
Started Jan 24 04:27:11 PM PST 24
Finished Jan 24 04:27:21 PM PST 24
Peak memory 229872 kb
Host smart-16950e26-323f-44b6-9e05-8d8cc1ef2ab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994170611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.994170611
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.588232391
Short name T136
Test name
Test status
Simulation time 78663114 ps
CPU time 1.49 seconds
Started Jan 24 04:27:09 PM PST 24
Finished Jan 24 04:27:17 PM PST 24
Peak memory 229848 kb
Host smart-a5264e0f-8b4c-4e32-a6a3-a5086a476561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588232391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.588232391
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.764713670
Short name T301
Test name
Test status
Simulation time 76647699 ps
CPU time 1.49 seconds
Started Jan 24 04:32:39 PM PST 24
Finished Jan 24 04:32:41 PM PST 24
Peak memory 229860 kb
Host smart-38c341f0-528d-4614-a60d-4a3e481e0535
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764713670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.764713670
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.37276860
Short name T363
Test name
Test status
Simulation time 77940131 ps
CPU time 1.37 seconds
Started Jan 24 04:27:12 PM PST 24
Finished Jan 24 04:27:24 PM PST 24
Peak memory 229888 kb
Host smart-fc3406f6-b765-4d2a-ab8c-70b74b008ddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37276860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.37276860
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.1826828054
Short name T388
Test name
Test status
Simulation time 37537761 ps
CPU time 1.36 seconds
Started Jan 24 07:08:26 PM PST 24
Finished Jan 24 07:08:33 PM PST 24
Peak memory 229848 kb
Host smart-3bc5f48d-fd3e-4218-8eee-1ea052147266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826828054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.1826828054
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.2465082008
Short name T302
Test name
Test status
Simulation time 131829325 ps
CPU time 1.45 seconds
Started Jan 24 04:27:24 PM PST 24
Finished Jan 24 04:27:31 PM PST 24
Peak memory 229840 kb
Host smart-865939a2-d3f4-49e3-a71b-6345e96be172
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465082008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.2465082008
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.3030959638
Short name T360
Test name
Test status
Simulation time 40521262 ps
CPU time 1.36 seconds
Started Jan 24 04:27:23 PM PST 24
Finished Jan 24 04:27:31 PM PST 24
Peak memory 229820 kb
Host smart-3be91576-f33f-48f3-8010-605cb07ade66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030959638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.3030959638
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.572961479
Short name T126
Test name
Test status
Simulation time 210128055 ps
CPU time 2.74 seconds
Started Jan 24 04:41:51 PM PST 24
Finished Jan 24 04:41:59 PM PST 24
Peak memory 229836 kb
Host smart-c5424f57-b8a3-41ce-81f4-1374c59f80ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572961479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alias
ing.572961479
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.220905087
Short name T110
Test name
Test status
Simulation time 479272268 ps
CPU time 9.19 seconds
Started Jan 24 04:25:32 PM PST 24
Finished Jan 24 04:25:43 PM PST 24
Peak memory 237924 kb
Host smart-b39d9a95-08da-4be8-8bca-eb6af148723f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220905087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_b
ash.220905087
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.3521380680
Short name T118
Test name
Test status
Simulation time 198848820 ps
CPU time 2.55 seconds
Started Jan 24 04:25:33 PM PST 24
Finished Jan 24 04:25:39 PM PST 24
Peak memory 229832 kb
Host smart-790bb3f8-2a82-42fe-94ff-b4edef4f2e9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521380680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.3521380680
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.329999269
Short name T307
Test name
Test status
Simulation time 86311398 ps
CPU time 1.52 seconds
Started Jan 24 05:57:59 PM PST 24
Finished Jan 24 05:58:03 PM PST 24
Peak memory 229764 kb
Host smart-387e4bbf-7c0c-4e35-b32a-19a5e6684721
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329999269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.329999269
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.834933835
Short name T356
Test name
Test status
Simulation time 36637685 ps
CPU time 1.34 seconds
Started Jan 24 04:32:48 PM PST 24
Finished Jan 24 04:32:50 PM PST 24
Peak memory 229824 kb
Host smart-13e34e55-f34f-4b61-9080-51ee84ceac27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834933835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.834933835
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.257699489
Short name T361
Test name
Test status
Simulation time 512335594 ps
CPU time 1.63 seconds
Started Jan 24 04:51:19 PM PST 24
Finished Jan 24 04:51:27 PM PST 24
Peak memory 229536 kb
Host smart-bf833e7d-e049-4366-981f-f6419c15e6ec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257699489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl
_mem_partial_access.257699489
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2419572861
Short name T369
Test name
Test status
Simulation time 34946729 ps
CPU time 1.3 seconds
Started Jan 24 04:25:33 PM PST 24
Finished Jan 24 04:25:37 PM PST 24
Peak memory 229560 kb
Host smart-5f001617-f317-4db4-a449-66e09bf603b8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419572861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.2419572861
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.2999756870
Short name T121
Test name
Test status
Simulation time 110675373 ps
CPU time 2.81 seconds
Started Jan 24 04:25:42 PM PST 24
Finished Jan 24 04:25:57 PM PST 24
Peak memory 239396 kb
Host smart-89235c40-a903-4670-974d-884a1f41050d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999756870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.2999756870
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.877125902
Short name T380
Test name
Test status
Simulation time 357883973 ps
CPU time 3.67 seconds
Started Jan 24 04:25:34 PM PST 24
Finished Jan 24 04:25:40 PM PST 24
Peak memory 238156 kb
Host smart-4a2a6554-543c-4ac0-a455-10a04acf778a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877125902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.877125902
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3642209352
Short name T141
Test name
Test status
Simulation time 609489612 ps
CPU time 9.21 seconds
Started Jan 24 04:25:33 PM PST 24
Finished Jan 24 04:25:44 PM PST 24
Peak memory 240920 kb
Host smart-90b02398-af1b-466e-88b9-ddbf812eaf0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642209352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in
tg_err.3642209352
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.3392260028
Short name T375
Test name
Test status
Simulation time 73832145 ps
CPU time 1.44 seconds
Started Jan 24 04:27:19 PM PST 24
Finished Jan 24 04:27:29 PM PST 24
Peak memory 229828 kb
Host smart-aca6b979-5bbc-49b6-bd2b-3046b1febe77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392260028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.3392260028
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.1068035740
Short name T424
Test name
Test status
Simulation time 40272473 ps
CPU time 1.39 seconds
Started Jan 24 04:27:20 PM PST 24
Finished Jan 24 04:27:29 PM PST 24
Peak memory 229828 kb
Host smart-21aedceb-1a5e-4dff-a845-ccd75466d2b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068035740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.1068035740
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.3274520627
Short name T133
Test name
Test status
Simulation time 48397815 ps
CPU time 1.35 seconds
Started Jan 24 04:27:28 PM PST 24
Finished Jan 24 04:27:32 PM PST 24
Peak memory 229820 kb
Host smart-99be0512-4255-4d88-b989-afad699b3234
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274520627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.3274520627
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.3663971673
Short name T373
Test name
Test status
Simulation time 137434734 ps
CPU time 1.57 seconds
Started Jan 24 04:27:28 PM PST 24
Finished Jan 24 04:27:32 PM PST 24
Peak memory 229876 kb
Host smart-ef0bb53b-459d-4508-bdb2-e5d9bb80f2e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663971673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.3663971673
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.2975557881
Short name T366
Test name
Test status
Simulation time 136328422 ps
CPU time 1.33 seconds
Started Jan 24 04:27:28 PM PST 24
Finished Jan 24 04:27:33 PM PST 24
Peak memory 229856 kb
Host smart-fe9ff352-4a03-450f-ba32-477e6f435830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975557881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.2975557881
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.554314028
Short name T431
Test name
Test status
Simulation time 68789277 ps
CPU time 1.32 seconds
Started Jan 24 04:27:30 PM PST 24
Finished Jan 24 04:27:34 PM PST 24
Peak memory 229872 kb
Host smart-0849e524-2d43-48f1-9ec1-0b18802d4f79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554314028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.554314028
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.721561285
Short name T400
Test name
Test status
Simulation time 51073682 ps
CPU time 1.39 seconds
Started Jan 24 04:27:30 PM PST 24
Finished Jan 24 04:27:34 PM PST 24
Peak memory 229824 kb
Host smart-4e7db057-a830-4446-b146-513ff365bf78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721561285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.721561285
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.3024264026
Short name T367
Test name
Test status
Simulation time 66762042 ps
CPU time 1.38 seconds
Started Jan 24 04:27:30 PM PST 24
Finished Jan 24 04:27:34 PM PST 24
Peak memory 229864 kb
Host smart-a5c7d496-da40-45e3-9148-19523498f080
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024264026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.3024264026
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2379001312
Short name T114
Test name
Test status
Simulation time 47260020 ps
CPU time 1.36 seconds
Started Jan 24 04:27:26 PM PST 24
Finished Jan 24 04:27:32 PM PST 24
Peak memory 229856 kb
Host smart-d091b2b7-8007-443c-a394-c8faf3d723fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379001312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.2379001312
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3743143594
Short name T143
Test name
Test status
Simulation time 71270742 ps
CPU time 1.41 seconds
Started Jan 24 04:27:28 PM PST 24
Finished Jan 24 04:27:33 PM PST 24
Peak memory 229864 kb
Host smart-f8b40389-c2b4-4d13-9a0e-508e13459a83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743143594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3743143594
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2717708048
Short name T374
Test name
Test status
Simulation time 138215748 ps
CPU time 2.6 seconds
Started Jan 24 04:25:54 PM PST 24
Finished Jan 24 04:26:04 PM PST 24
Peak memory 238136 kb
Host smart-721ea94b-5d79-42d4-9919-cea26b01becb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717708048 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.2717708048
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.1455035298
Short name T306
Test name
Test status
Simulation time 133410426 ps
CPU time 1.54 seconds
Started Jan 24 04:29:22 PM PST 24
Finished Jan 24 04:29:25 PM PST 24
Peak memory 229768 kb
Host smart-d0d34015-1cac-4eec-b279-ecb1e9c36080
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455035298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.1455035298
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.602299439
Short name T318
Test name
Test status
Simulation time 552565550 ps
CPU time 1.44 seconds
Started Jan 24 04:25:41 PM PST 24
Finished Jan 24 04:25:56 PM PST 24
Peak memory 229792 kb
Host smart-ce6eb008-0154-43d9-80e9-be3ac2d3eec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602299439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.602299439
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1779122468
Short name T282
Test name
Test status
Simulation time 160655611 ps
CPU time 1.97 seconds
Started Jan 24 04:25:53 PM PST 24
Finished Jan 24 04:26:04 PM PST 24
Peak memory 238120 kb
Host smart-b7db0ba1-6b28-46c6-86e5-c64e49a5f918
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779122468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.1779122468
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.1642321571
Short name T378
Test name
Test status
Simulation time 99114538 ps
CPU time 2.83 seconds
Started Jan 24 04:25:43 PM PST 24
Finished Jan 24 04:25:57 PM PST 24
Peak memory 243656 kb
Host smart-402be94f-3b50-44f2-bf25-c5aac40ec2e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642321571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.1642321571
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1934007195
Short name T90
Test name
Test status
Simulation time 69033771 ps
CPU time 2.52 seconds
Started Jan 24 04:25:53 PM PST 24
Finished Jan 24 04:26:04 PM PST 24
Peak memory 238120 kb
Host smart-3e953321-f1af-4fb9-adca-0faf349b4dba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934007195 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.1934007195
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.201196803
Short name T299
Test name
Test status
Simulation time 38966899 ps
CPU time 1.53 seconds
Started Jan 24 04:25:49 PM PST 24
Finished Jan 24 04:26:00 PM PST 24
Peak memory 229828 kb
Host smart-c9784932-1eaa-4066-a832-f4fe419954bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201196803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.201196803
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.3325487383
Short name T435
Test name
Test status
Simulation time 43313465 ps
CPU time 1.33 seconds
Started Jan 24 04:25:49 PM PST 24
Finished Jan 24 04:26:00 PM PST 24
Peak memory 229812 kb
Host smart-46c2c203-d4b7-41d0-8d56-e0b24d96cd0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325487383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.3325487383
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.2680256105
Short name T385
Test name
Test status
Simulation time 51763932 ps
CPU time 1.93 seconds
Started Jan 24 04:25:52 PM PST 24
Finished Jan 24 04:26:03 PM PST 24
Peak memory 230012 kb
Host smart-ef6549f4-26fb-465c-be42-715dbc9cca79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680256105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.2680256105
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.2886604510
Short name T432
Test name
Test status
Simulation time 404404665 ps
CPU time 4.03 seconds
Started Jan 24 04:25:50 PM PST 24
Finished Jan 24 04:26:03 PM PST 24
Peak memory 244288 kb
Host smart-a584a5ad-a2f1-479c-b0c3-916723c3e002
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886604510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.2886604510
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1336671642
Short name T379
Test name
Test status
Simulation time 627153834 ps
CPU time 8.84 seconds
Started Jan 24 04:25:51 PM PST 24
Finished Jan 24 04:26:09 PM PST 24
Peak memory 240800 kb
Host smart-27a96bb8-f282-4f31-be31-9b1c12c22cd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336671642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.1336671642
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.459361147
Short name T370
Test name
Test status
Simulation time 219344441 ps
CPU time 2.94 seconds
Started Jan 24 04:33:55 PM PST 24
Finished Jan 24 04:34:00 PM PST 24
Peak memory 238220 kb
Host smart-ef687968-e290-4887-a499-941f4c0a2fd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459361147 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.459361147
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.4278415295
Short name T308
Test name
Test status
Simulation time 53409090 ps
CPU time 1.59 seconds
Started Jan 24 04:25:49 PM PST 24
Finished Jan 24 04:26:00 PM PST 24
Peak memory 229772 kb
Host smart-51328d27-6b37-4ad6-b830-af14d7d0d695
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278415295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.4278415295
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.4099212298
Short name T372
Test name
Test status
Simulation time 69001298 ps
CPU time 1.46 seconds
Started Jan 24 04:25:52 PM PST 24
Finished Jan 24 04:26:02 PM PST 24
Peak memory 229800 kb
Host smart-c43b0464-467b-41b4-9aef-9a94e29c5064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099212298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.4099212298
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1763164504
Short name T113
Test name
Test status
Simulation time 1945184575 ps
CPU time 4.19 seconds
Started Jan 24 04:25:48 PM PST 24
Finished Jan 24 04:26:02 PM PST 24
Peak memory 238028 kb
Host smart-f5885193-7ae2-4f0e-b670-b592bb7344f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763164504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c
trl_same_csr_outstanding.1763164504
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3160818922
Short name T406
Test name
Test status
Simulation time 81933221 ps
CPU time 4.3 seconds
Started Jan 24 04:25:51 PM PST 24
Finished Jan 24 04:26:04 PM PST 24
Peak memory 238200 kb
Host smart-6e6e44b3-aa65-417c-b576-e713dd80433d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160818922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3160818922
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.2149651681
Short name T421
Test name
Test status
Simulation time 634679524 ps
CPU time 9.97 seconds
Started Jan 24 04:25:49 PM PST 24
Finished Jan 24 04:26:08 PM PST 24
Peak memory 240688 kb
Host smart-42162072-5577-4bff-8efa-cd5f742f64ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149651681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in
tg_err.2149651681
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.122424225
Short name T129
Test name
Test status
Simulation time 71982172 ps
CPU time 2.9 seconds
Started Jan 24 04:25:59 PM PST 24
Finished Jan 24 04:26:06 PM PST 24
Peak memory 238004 kb
Host smart-80f82b95-4950-4fec-a375-9f9aaf0da9a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122424225 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.122424225
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.4127219756
Short name T298
Test name
Test status
Simulation time 71435756 ps
CPU time 1.45 seconds
Started Jan 24 04:25:59 PM PST 24
Finished Jan 24 04:26:05 PM PST 24
Peak memory 229812 kb
Host smart-69002d10-21de-42a3-ba15-8edd055d09e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127219756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.4127219756
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.1234239646
Short name T317
Test name
Test status
Simulation time 141921106 ps
CPU time 1.36 seconds
Started Jan 24 05:06:19 PM PST 24
Finished Jan 24 05:06:34 PM PST 24
Peak memory 229884 kb
Host smart-e6dd3eca-345b-4176-8f6f-45cc6ec62ab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234239646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.1234239646
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.902525683
Short name T413
Test name
Test status
Simulation time 50708085 ps
CPU time 1.8 seconds
Started Jan 24 05:06:40 PM PST 24
Finished Jan 24 05:06:46 PM PST 24
Peak memory 238064 kb
Host smart-df28724a-8d3e-4696-b739-f799f660aefa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902525683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ct
rl_same_csr_outstanding.902525683
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.1690640522
Short name T278
Test name
Test status
Simulation time 81466290 ps
CPU time 5.24 seconds
Started Jan 24 04:26:04 PM PST 24
Finished Jan 24 04:26:12 PM PST 24
Peak memory 238216 kb
Host smart-bce9d070-a482-4128-b019-79ff9da2f0ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690640522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.1690640522
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2886014667
Short name T316
Test name
Test status
Simulation time 4592344622 ps
CPU time 16.58 seconds
Started Jan 24 04:26:05 PM PST 24
Finished Jan 24 04:26:24 PM PST 24
Peak memory 242016 kb
Host smart-745f0d67-e542-4907-a1c6-8a8a9427f70c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886014667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.2886014667
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.3810583567
Short name T418
Test name
Test status
Simulation time 97807291 ps
CPU time 3.18 seconds
Started Jan 24 04:26:06 PM PST 24
Finished Jan 24 04:26:11 PM PST 24
Peak memory 238176 kb
Host smart-388ca898-57fe-4040-9103-6f3a52a72997
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810583567 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.3810583567
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3635848284
Short name T295
Test name
Test status
Simulation time 547191203 ps
CPU time 1.77 seconds
Started Jan 24 04:26:00 PM PST 24
Finished Jan 24 04:26:06 PM PST 24
Peak memory 229840 kb
Host smart-c0be1146-48c1-4ba9-96ed-f0d02495d354
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635848284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.3635848284
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.4274539123
Short name T132
Test name
Test status
Simulation time 162638190 ps
CPU time 1.41 seconds
Started Jan 24 04:44:37 PM PST 24
Finished Jan 24 04:44:39 PM PST 24
Peak memory 229852 kb
Host smart-7f284b6a-f2e0-456c-a185-b22597cc26ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274539123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.4274539123
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.1116621254
Short name T398
Test name
Test status
Simulation time 83975199 ps
CPU time 2.44 seconds
Started Jan 24 04:26:04 PM PST 24
Finished Jan 24 04:26:09 PM PST 24
Peak memory 238260 kb
Host smart-3a889b47-78e3-4517-88a9-80bda1d68345
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116621254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.1116621254
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.431653992
Short name T357
Test name
Test status
Simulation time 347923241 ps
CPU time 6.45 seconds
Started Jan 24 07:09:59 PM PST 24
Finished Jan 24 07:10:07 PM PST 24
Peak memory 238140 kb
Host smart-59aa1f3c-a19f-4747-8616-5765f7cd9813
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431653992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.431653992
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.2318613525
Short name T411
Test name
Test status
Simulation time 9447463706 ps
CPU time 11.78 seconds
Started Jan 24 04:26:04 PM PST 24
Finished Jan 24 04:26:19 PM PST 24
Peak memory 241548 kb
Host smart-35288f68-7181-47e6-89a8-3bc9b0ac5254
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318613525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.2318613525
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.1241537012
Short name T592
Test name
Test status
Simulation time 85005543 ps
CPU time 2 seconds
Started Jan 24 09:14:44 PM PST 24
Finished Jan 24 09:14:47 PM PST 24
Peak memory 240036 kb
Host smart-6cf76208-992a-4ed5-a387-67cae27df8a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241537012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.1241537012
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.3378125111
Short name T144
Test name
Test status
Simulation time 7864338630 ps
CPU time 20.89 seconds
Started Jan 24 09:49:40 PM PST 24
Finished Jan 24 09:50:02 PM PST 24
Peak memory 244180 kb
Host smart-4f70f609-0131-4b72-8b81-14a0cf45f556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378125111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.3378125111
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.1021716222
Short name T157
Test name
Test status
Simulation time 9906554332 ps
CPU time 29.68 seconds
Started Jan 24 08:53:04 PM PST 24
Finished Jan 24 08:53:35 PM PST 24
Peak memory 239680 kb
Host smart-151ae487-a5a9-46c3-9a17-5b434e94eae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021716222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.1021716222
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.4175111468
Short name T469
Test name
Test status
Simulation time 235936125 ps
CPU time 4.05 seconds
Started Jan 24 08:53:21 PM PST 24
Finished Jan 24 08:53:26 PM PST 24
Peak memory 246292 kb
Host smart-9fdf0b30-18e6-4810-a8ff-0f09d63913ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4175111468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.4175111468
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.377363284
Short name T16
Test name
Test status
Simulation time 131373509793 ps
CPU time 230.94 seconds
Started Jan 24 08:53:24 PM PST 24
Finished Jan 24 08:57:16 PM PST 24
Peak memory 261172 kb
Host smart-a6b9d5ca-74dc-4d8b-922e-3d982504a24d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377363284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.377363284
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.1702723389
Short name T159
Test name
Test status
Simulation time 66928989 ps
CPU time 1.84 seconds
Started Jan 24 09:18:12 PM PST 24
Finished Jan 24 09:18:15 PM PST 24
Peak memory 230728 kb
Host smart-4ff8a1a0-35d4-41db-bb23-d47fe335fa64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1702723389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.1702723389
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.3506029592
Short name T622
Test name
Test status
Simulation time 77672970 ps
CPU time 2.04 seconds
Started Jan 24 08:53:59 PM PST 24
Finished Jan 24 08:54:03 PM PST 24
Peak memory 239852 kb
Host smart-4dbaf1c5-14c8-4eb8-8594-13ef2c67db7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506029592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.3506029592
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.3431813707
Short name T614
Test name
Test status
Simulation time 548609795 ps
CPU time 4.61 seconds
Started Jan 24 08:53:28 PM PST 24
Finished Jan 24 08:53:33 PM PST 24
Peak memory 244040 kb
Host smart-11404193-f16a-4d8e-86dd-9f6934a7d5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431813707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.3431813707
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.2999741927
Short name T512
Test name
Test status
Simulation time 127360397 ps
CPU time 3.5 seconds
Started Jan 24 08:53:59 PM PST 24
Finished Jan 24 08:54:03 PM PST 24
Peak memory 243664 kb
Host smart-2dabd27f-0226-439b-91b6-7320cb06ad0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2999741927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.2999741927
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.413783523
Short name T15
Test name
Test status
Simulation time 20634963916 ps
CPU time 159.2 seconds
Started Jan 24 08:53:53 PM PST 24
Finished Jan 24 08:56:34 PM PST 24
Peak memory 273060 kb
Host smart-b9a55b8b-958d-44ba-80b6-62c3f03d6425
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413783523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.413783523
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.2227313758
Short name T312
Test name
Test status
Simulation time 449355143 ps
CPU time 6.28 seconds
Started Jan 24 08:53:24 PM PST 24
Finished Jan 24 08:53:31 PM PST 24
Peak memory 239580 kb
Host smart-0fe379b3-c4e9-4d97-ad27-1ecfd3929696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227313758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.2227313758
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.1942130405
Short name T341
Test name
Test status
Simulation time 719023603 ps
CPU time 1.91 seconds
Started Jan 24 08:56:33 PM PST 24
Finished Jan 24 08:56:36 PM PST 24
Peak memory 239708 kb
Host smart-d8901f1b-392a-489b-9256-31f848fad319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942130405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.1942130405
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.3885159956
Short name T583
Test name
Test status
Simulation time 157504362 ps
CPU time 4.15 seconds
Started Jan 24 09:03:07 PM PST 24
Finished Jan 24 09:03:12 PM PST 24
Peak memory 243696 kb
Host smart-89dd8169-6e2c-49d8-8a32-c758e0e52285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885159956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.3885159956
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.1613061712
Short name T204
Test name
Test status
Simulation time 686534559 ps
CPU time 8.33 seconds
Started Jan 24 08:56:23 PM PST 24
Finished Jan 24 08:56:32 PM PST 24
Peak memory 245700 kb
Host smart-1396c07a-695f-475a-b870-ff7ffb2ca03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613061712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.1613061712
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.3454076511
Short name T168
Test name
Test status
Simulation time 232037571 ps
CPU time 3.33 seconds
Started Jan 24 09:11:00 PM PST 24
Finished Jan 24 09:11:07 PM PST 24
Peak memory 239524 kb
Host smart-79497c0e-fb50-4d2c-99eb-48dacae2025b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454076511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.3454076511
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.1181803953
Short name T636
Test name
Test status
Simulation time 222765274 ps
CPU time 3.71 seconds
Started Jan 24 09:52:05 PM PST 24
Finished Jan 24 09:52:10 PM PST 24
Peak memory 239588 kb
Host smart-4d873eca-69fd-4ad1-ade0-18a351d0d96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181803953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.1181803953
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.2279605163
Short name T255
Test name
Test status
Simulation time 239903557 ps
CPU time 5.25 seconds
Started Jan 24 09:10:58 PM PST 24
Finished Jan 24 09:11:05 PM PST 24
Peak memory 243972 kb
Host smart-a69fec31-e7ea-4fef-b255-1befe7074cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279605163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.2279605163
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.3120774365
Short name T666
Test name
Test status
Simulation time 106537988 ps
CPU time 2.88 seconds
Started Jan 24 09:10:59 PM PST 24
Finished Jan 24 09:11:05 PM PST 24
Peak memory 244088 kb
Host smart-454c940f-af59-4a97-a2c0-8de57404522d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120774365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.3120774365
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.4272917578
Short name T676
Test name
Test status
Simulation time 200373890 ps
CPU time 3.26 seconds
Started Jan 24 09:10:55 PM PST 24
Finished Jan 24 09:11:00 PM PST 24
Peak memory 243564 kb
Host smart-15c9f0fd-f3d6-4385-b2e0-3f439fd53ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272917578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.4272917578
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.3431637674
Short name T59
Test name
Test status
Simulation time 96583478 ps
CPU time 3.43 seconds
Started Jan 24 09:10:59 PM PST 24
Finished Jan 24 09:11:06 PM PST 24
Peak memory 244112 kb
Host smart-1bda4657-add4-479d-91e2-9c93ea98b621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431637674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.3431637674
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.3548351832
Short name T715
Test name
Test status
Simulation time 219547256 ps
CPU time 6.29 seconds
Started Jan 24 09:11:00 PM PST 24
Finished Jan 24 09:11:09 PM PST 24
Peak memory 245268 kb
Host smart-19adf6ad-5616-4090-8ba3-1306bab51665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548351832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.3548351832
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.3717003259
Short name T581
Test name
Test status
Simulation time 271061011 ps
CPU time 3.65 seconds
Started Jan 24 09:43:54 PM PST 24
Finished Jan 24 09:43:59 PM PST 24
Peak memory 243336 kb
Host smart-5c09ed2c-517b-4aba-be32-59614e0d9f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717003259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.3717003259
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.1562110285
Short name T552
Test name
Test status
Simulation time 147962990 ps
CPU time 3.61 seconds
Started Jan 24 09:10:56 PM PST 24
Finished Jan 24 09:11:01 PM PST 24
Peak memory 244024 kb
Host smart-e9a6ac43-e6ee-4afb-a6bd-af711f5ad688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562110285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.1562110285
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.2133711283
Short name T699
Test name
Test status
Simulation time 1473752701 ps
CPU time 4.56 seconds
Started Jan 24 09:11:01 PM PST 24
Finished Jan 24 09:11:08 PM PST 24
Peak memory 242976 kb
Host smart-b343f8e5-0e55-45b2-9696-d70116c023b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133711283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.2133711283
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.4037810458
Short name T179
Test name
Test status
Simulation time 59723013 ps
CPU time 1.69 seconds
Started Jan 24 08:56:48 PM PST 24
Finished Jan 24 08:56:51 PM PST 24
Peak memory 239760 kb
Host smart-1f90eb50-0896-46e9-ae87-d362739b388f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037810458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.4037810458
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.3976829620
Short name T554
Test name
Test status
Simulation time 467350389 ps
CPU time 3.72 seconds
Started Jan 24 08:56:41 PM PST 24
Finished Jan 24 08:56:46 PM PST 24
Peak memory 243460 kb
Host smart-4ec4e208-c044-4d0c-86b3-22e507ac16cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976829620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.3976829620
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.770350793
Short name T556
Test name
Test status
Simulation time 356600507 ps
CPU time 5.65 seconds
Started Jan 24 09:06:47 PM PST 24
Finished Jan 24 09:06:53 PM PST 24
Peak memory 243684 kb
Host smart-84abf13f-ca32-40f0-b170-527935eb9a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770350793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.770350793
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.3486426965
Short name T537
Test name
Test status
Simulation time 130890188 ps
CPU time 3.6 seconds
Started Jan 24 11:05:28 PM PST 24
Finished Jan 24 11:05:33 PM PST 24
Peak memory 243396 kb
Host smart-e4a3decf-4868-4e9d-ae63-bfb9d9919176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486426965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.3486426965
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.1250607397
Short name T623
Test name
Test status
Simulation time 2557002817 ps
CPU time 4.73 seconds
Started Jan 25 12:39:19 AM PST 24
Finished Jan 25 12:39:25 AM PST 24
Peak memory 245020 kb
Host smart-5082375f-dad3-4dd0-93ec-1794d270f411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250607397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.1250607397
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.3755032075
Short name T101
Test name
Test status
Simulation time 1471886112 ps
CPU time 19.75 seconds
Started Jan 24 09:10:59 PM PST 24
Finished Jan 24 09:11:22 PM PST 24
Peak memory 247516 kb
Host smart-4c70579b-186b-48ee-ac9d-b3b14fe42e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755032075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.3755032075
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.1002152161
Short name T175
Test name
Test status
Simulation time 128518763 ps
CPU time 3.41 seconds
Started Jan 24 10:13:17 PM PST 24
Finished Jan 24 10:13:23 PM PST 24
Peak memory 243968 kb
Host smart-dcb6da17-6a8d-42ed-b7ef-0de279325023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002152161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.1002152161
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.2524618441
Short name T531
Test name
Test status
Simulation time 134725929 ps
CPU time 3.33 seconds
Started Jan 24 09:11:16 PM PST 24
Finished Jan 24 09:11:21 PM PST 24
Peak memory 242572 kb
Host smart-910dc4f9-38fd-4bec-b68c-569a4b4dc385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524618441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.2524618441
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.3988220689
Short name T697
Test name
Test status
Simulation time 2672460003 ps
CPU time 5.98 seconds
Started Jan 24 09:11:24 PM PST 24
Finished Jan 24 09:11:31 PM PST 24
Peak memory 243572 kb
Host smart-9abc576b-5af2-467d-91b0-c34c18a1ec0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988220689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.3988220689
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.1622499989
Short name T26
Test name
Test status
Simulation time 326450554 ps
CPU time 3.68 seconds
Started Jan 24 09:11:16 PM PST 24
Finished Jan 24 09:11:21 PM PST 24
Peak memory 239536 kb
Host smart-22538893-a698-4770-b340-69bab2459f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622499989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.1622499989
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.524815768
Short name T187
Test name
Test status
Simulation time 698250387 ps
CPU time 5.49 seconds
Started Jan 24 09:11:33 PM PST 24
Finished Jan 24 09:11:39 PM PST 24
Peak memory 239524 kb
Host smart-c495a1ae-cd83-4bec-9084-f8ad6802b665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524815768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.524815768
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.1251392925
Short name T257
Test name
Test status
Simulation time 147630788 ps
CPU time 2.6 seconds
Started Jan 24 09:11:28 PM PST 24
Finished Jan 24 09:11:32 PM PST 24
Peak memory 239604 kb
Host smart-2dfcdc8e-134c-4f3f-b160-72cae58ec44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251392925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.1251392925
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.2077209055
Short name T279
Test name
Test status
Simulation time 119433186 ps
CPU time 2.16 seconds
Started Jan 24 08:56:48 PM PST 24
Finished Jan 24 08:56:52 PM PST 24
Peak memory 239396 kb
Host smart-6ed2470c-b5d3-4cad-ad5f-f06c0d87f09f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077209055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.2077209055
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.1830559847
Short name T677
Test name
Test status
Simulation time 124306041 ps
CPU time 4.42 seconds
Started Jan 24 08:58:12 PM PST 24
Finished Jan 24 08:58:20 PM PST 24
Peak memory 243240 kb
Host smart-1490ad95-913b-4388-a178-20a02c50c3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830559847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.1830559847
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.2529071933
Short name T222
Test name
Test status
Simulation time 188050322 ps
CPU time 5.51 seconds
Started Jan 24 08:56:51 PM PST 24
Finished Jan 24 08:56:58 PM PST 24
Peak memory 239548 kb
Host smart-cf2b79ea-f09f-410d-886c-fe535e33c5a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2529071933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2529071933
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.1886155365
Short name T655
Test name
Test status
Simulation time 459092974 ps
CPU time 3.36 seconds
Started Jan 24 09:11:28 PM PST 24
Finished Jan 24 09:11:33 PM PST 24
Peak memory 243976 kb
Host smart-6e245e9c-a56c-41ec-ab8b-d9a3cead9fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886155365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.1886155365
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.1465098776
Short name T165
Test name
Test status
Simulation time 234132482 ps
CPU time 4.64 seconds
Started Jan 24 09:11:30 PM PST 24
Finished Jan 24 09:11:36 PM PST 24
Peak memory 244688 kb
Host smart-f652dca8-8bf5-405e-90c0-33237d5c9da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465098776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.1465098776
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.3839105303
Short name T145
Test name
Test status
Simulation time 1941831755 ps
CPU time 4.85 seconds
Started Jan 24 09:11:28 PM PST 24
Finished Jan 24 09:11:34 PM PST 24
Peak memory 244528 kb
Host smart-41a9a7d9-73a4-489f-93ec-31f0b2c967d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839105303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.3839105303
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.3833932046
Short name T701
Test name
Test status
Simulation time 453254568 ps
CPU time 3.26 seconds
Started Jan 24 09:11:49 PM PST 24
Finished Jan 24 09:11:53 PM PST 24
Peak memory 239536 kb
Host smart-ada3492d-a1da-462c-97e1-1f583e1fe66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833932046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.3833932046
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.2187201621
Short name T347
Test name
Test status
Simulation time 151728444 ps
CPU time 4.27 seconds
Started Jan 24 09:11:54 PM PST 24
Finished Jan 24 09:11:59 PM PST 24
Peak memory 239528 kb
Host smart-f0ccd1b3-1dee-4fee-b3ec-898a4bb459f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187201621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.2187201621
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.3796643888
Short name T620
Test name
Test status
Simulation time 159683194 ps
CPU time 3.73 seconds
Started Jan 24 09:11:50 PM PST 24
Finished Jan 24 09:11:54 PM PST 24
Peak memory 243284 kb
Host smart-cb51db64-0602-428b-a38b-a2a425a03ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796643888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.3796643888
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.2100352241
Short name T700
Test name
Test status
Simulation time 180579031 ps
CPU time 3.92 seconds
Started Jan 24 09:11:50 PM PST 24
Finished Jan 24 09:11:55 PM PST 24
Peak memory 243668 kb
Host smart-65051883-b189-4732-be99-9614cb5784ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100352241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.2100352241
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.619645582
Short name T74
Test name
Test status
Simulation time 353867975 ps
CPU time 3.72 seconds
Started Jan 24 09:11:49 PM PST 24
Finished Jan 24 09:11:54 PM PST 24
Peak memory 242604 kb
Host smart-c5fd2e89-17c7-42b7-a0ed-dede80f7ad4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619645582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.619645582
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.1456038651
Short name T541
Test name
Test status
Simulation time 1148978075 ps
CPU time 9.34 seconds
Started Jan 24 09:11:49 PM PST 24
Finished Jan 24 09:11:59 PM PST 24
Peak memory 246600 kb
Host smart-43b3418e-83ce-4f12-8348-f42238ae0f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456038651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.1456038651
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.3533954716
Short name T599
Test name
Test status
Simulation time 804540061 ps
CPU time 2.48 seconds
Started Jan 24 08:57:06 PM PST 24
Finished Jan 24 08:57:11 PM PST 24
Peak memory 239900 kb
Host smart-52f751d9-a21f-4bba-8bc9-ca19b927e6e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533954716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.3533954716
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.1329646261
Short name T163
Test name
Test status
Simulation time 421030391 ps
CPU time 3.42 seconds
Started Jan 24 08:57:05 PM PST 24
Finished Jan 24 08:57:11 PM PST 24
Peak memory 239480 kb
Host smart-869cf578-91c5-43e4-8c66-54dfe8f241ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329646261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.1329646261
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.1654425710
Short name T192
Test name
Test status
Simulation time 1316038459 ps
CPU time 16.26 seconds
Started Jan 24 08:57:01 PM PST 24
Finished Jan 24 08:57:19 PM PST 24
Peak memory 247680 kb
Host smart-529973d8-d3e4-4504-a3af-1ce1fa5bcb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654425710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.1654425710
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.1051134353
Short name T220
Test name
Test status
Simulation time 254434675 ps
CPU time 7.74 seconds
Started Jan 24 08:57:07 PM PST 24
Finished Jan 24 08:57:20 PM PST 24
Peak memory 239624 kb
Host smart-eb79fee7-b90f-4e71-9af0-351fa87d99f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051134353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.1051134353
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.1616443142
Short name T213
Test name
Test status
Simulation time 1407042929 ps
CPU time 8.95 seconds
Started Jan 24 08:56:46 PM PST 24
Finished Jan 24 08:56:56 PM PST 24
Peak memory 239600 kb
Host smart-157f9820-04d0-4fdb-a95d-7a66df5c4c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616443142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.1616443142
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.1907882382
Short name T577
Test name
Test status
Simulation time 389141793 ps
CPU time 4.16 seconds
Started Jan 24 09:11:51 PM PST 24
Finished Jan 24 09:11:56 PM PST 24
Peak memory 243264 kb
Host smart-deec6eb5-69c5-4d30-a2ab-225da1a5f0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907882382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.1907882382
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.3153628513
Short name T555
Test name
Test status
Simulation time 302911611 ps
CPU time 8 seconds
Started Jan 24 09:11:53 PM PST 24
Finished Jan 24 09:12:02 PM PST 24
Peak memory 245468 kb
Host smart-bc38e2e4-d554-4f4d-9583-92ce7c93087b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153628513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.3153628513
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.1354158687
Short name T510
Test name
Test status
Simulation time 348300547 ps
CPU time 5.16 seconds
Started Jan 24 09:11:53 PM PST 24
Finished Jan 24 09:11:59 PM PST 24
Peak memory 239548 kb
Host smart-5239d5a6-9eae-4ece-b1f1-33f13bbf0cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354158687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.1354158687
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.2298111313
Short name T3
Test name
Test status
Simulation time 236815969 ps
CPU time 3.65 seconds
Started Jan 24 09:11:54 PM PST 24
Finished Jan 24 09:11:59 PM PST 24
Peak memory 243508 kb
Host smart-6a3e01fa-9e2c-4f7e-9e15-04c5e6c98e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298111313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.2298111313
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.3537671477
Short name T170
Test name
Test status
Simulation time 2358395854 ps
CPU time 4.75 seconds
Started Jan 24 09:11:53 PM PST 24
Finished Jan 24 09:11:59 PM PST 24
Peak memory 244080 kb
Host smart-e29e3a55-c5bc-45de-ab41-b0abd3637322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537671477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.3537671477
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.3404650818
Short name T522
Test name
Test status
Simulation time 465105175 ps
CPU time 7.25 seconds
Started Jan 24 09:11:55 PM PST 24
Finished Jan 24 09:12:04 PM PST 24
Peak memory 245512 kb
Host smart-bde9b6f6-36fc-474b-afe7-1ba2c7e85f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404650818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.3404650818
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.2496433908
Short name T171
Test name
Test status
Simulation time 514389059 ps
CPU time 3.92 seconds
Started Jan 24 09:11:54 PM PST 24
Finished Jan 24 09:11:59 PM PST 24
Peak memory 242336 kb
Host smart-90a4a864-4bc8-457f-90d7-576d5a3eb0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496433908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.2496433908
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.1006557737
Short name T462
Test name
Test status
Simulation time 623709947 ps
CPU time 4.76 seconds
Started Jan 24 09:11:54 PM PST 24
Finished Jan 24 09:12:00 PM PST 24
Peak memory 243316 kb
Host smart-f17807f0-f992-4b5a-9167-0b834ec4bdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006557737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.1006557737
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.2140449159
Short name T323
Test name
Test status
Simulation time 223980595 ps
CPU time 6.26 seconds
Started Jan 24 09:56:04 PM PST 24
Finished Jan 24 09:56:11 PM PST 24
Peak memory 244440 kb
Host smart-cb2f5a55-af82-4bbf-860a-d4490f1b6751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140449159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.2140449159
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.1183649904
Short name T475
Test name
Test status
Simulation time 149517653 ps
CPU time 3.67 seconds
Started Jan 24 10:42:07 PM PST 24
Finished Jan 24 10:42:12 PM PST 24
Peak memory 239528 kb
Host smart-ba40bfdb-5026-4704-b52e-383bd6fe82d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183649904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.1183649904
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.1525114957
Short name T254
Test name
Test status
Simulation time 510938715 ps
CPU time 5.92 seconds
Started Jan 24 11:19:08 PM PST 24
Finished Jan 24 11:19:15 PM PST 24
Peak memory 239604 kb
Host smart-114d2a2b-6acf-4ab1-8369-1da3fa6023db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525114957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.1525114957
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.2668944917
Short name T470
Test name
Test status
Simulation time 1783747804 ps
CPU time 7.11 seconds
Started Jan 24 09:12:05 PM PST 24
Finished Jan 24 09:12:13 PM PST 24
Peak memory 243552 kb
Host smart-6523c849-58d0-4486-a2b5-27cb4cb4adad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668944917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.2668944917
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.259568568
Short name T350
Test name
Test status
Simulation time 155732028 ps
CPU time 3.97 seconds
Started Jan 25 12:22:14 AM PST 24
Finished Jan 25 12:22:21 AM PST 24
Peak memory 239544 kb
Host smart-60bb9e3b-38e8-468d-883a-19ae1495cf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259568568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.259568568
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.490661791
Short name T618
Test name
Test status
Simulation time 1909430096 ps
CPU time 4.63 seconds
Started Jan 24 09:12:08 PM PST 24
Finished Jan 24 09:12:13 PM PST 24
Peak memory 243948 kb
Host smart-081a4ad1-1639-45b8-968b-e967c50f7687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490661791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.490661791
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.2156724419
Short name T515
Test name
Test status
Simulation time 278526704 ps
CPU time 4.2 seconds
Started Jan 25 12:02:18 AM PST 24
Finished Jan 25 12:02:23 AM PST 24
Peak memory 239520 kb
Host smart-560d3432-d309-48ec-a303-905c11afeb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156724419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2156724419
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.827002747
Short name T637
Test name
Test status
Simulation time 785440707 ps
CPU time 1.95 seconds
Started Jan 24 08:57:40 PM PST 24
Finished Jan 24 08:57:44 PM PST 24
Peak memory 239772 kb
Host smart-44cdd4dc-d3b9-40d4-b6bb-a3721dc33ba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827002747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.827002747
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.3373076212
Short name T440
Test name
Test status
Simulation time 179502935 ps
CPU time 4.08 seconds
Started Jan 24 08:57:06 PM PST 24
Finished Jan 24 08:57:13 PM PST 24
Peak memory 239552 kb
Host smart-398a5cb1-06d2-46c8-b7d1-26f7dd4d1973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373076212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.3373076212
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.1857007298
Short name T266
Test name
Test status
Simulation time 464018967 ps
CPU time 4.07 seconds
Started Jan 24 08:57:15 PM PST 24
Finished Jan 24 08:57:20 PM PST 24
Peak memory 239596 kb
Host smart-bb9b28b8-a300-40ea-846c-044bcebe93c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857007298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.1857007298
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.2273056644
Short name T710
Test name
Test status
Simulation time 758384864 ps
CPU time 7.11 seconds
Started Jan 24 08:57:16 PM PST 24
Finished Jan 24 08:57:24 PM PST 24
Peak memory 239608 kb
Host smart-053f3696-33c7-42a3-b4aa-618b75579500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2273056644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.2273056644
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.2397283622
Short name T575
Test name
Test status
Simulation time 545278848 ps
CPU time 3.79 seconds
Started Jan 24 09:16:55 PM PST 24
Finished Jan 24 09:17:01 PM PST 24
Peak memory 239552 kb
Host smart-a3ced8bb-7d93-4c04-bb5c-da80ad4f80d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397283622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.2397283622
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.3558169847
Short name T353
Test name
Test status
Simulation time 568583986 ps
CPU time 4 seconds
Started Jan 24 09:12:12 PM PST 24
Finished Jan 24 09:12:17 PM PST 24
Peak memory 243376 kb
Host smart-80366cdb-078a-4636-a5b9-5ecbbce53a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558169847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.3558169847
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.1348070026
Short name T57
Test name
Test status
Simulation time 185701232 ps
CPU time 4.03 seconds
Started Jan 24 09:12:09 PM PST 24
Finished Jan 24 09:12:15 PM PST 24
Peak memory 244256 kb
Host smart-94c4562f-ee15-42e3-9b5b-37efdb5d62d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348070026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.1348070026
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.25385490
Short name T58
Test name
Test status
Simulation time 297550496 ps
CPU time 4.02 seconds
Started Jan 24 09:12:05 PM PST 24
Finished Jan 24 09:12:10 PM PST 24
Peak memory 243320 kb
Host smart-1c66f8b9-a210-4358-beac-5184c2518d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25385490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.25385490
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.723777624
Short name T694
Test name
Test status
Simulation time 591676309 ps
CPU time 4.16 seconds
Started Jan 24 09:12:12 PM PST 24
Finished Jan 24 09:12:17 PM PST 24
Peak memory 243288 kb
Host smart-14b65b2d-9110-4d94-bd53-826be3c6e9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723777624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.723777624
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.928928256
Short name T437
Test name
Test status
Simulation time 147911954 ps
CPU time 4.72 seconds
Started Jan 24 09:12:09 PM PST 24
Finished Jan 24 09:12:16 PM PST 24
Peak memory 239544 kb
Host smart-52376ca9-4c9a-47a6-b64b-363282d80d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928928256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.928928256
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.1378232757
Short name T709
Test name
Test status
Simulation time 2264256822 ps
CPU time 17.47 seconds
Started Jan 24 09:12:05 PM PST 24
Finished Jan 24 09:12:23 PM PST 24
Peak memory 247852 kb
Host smart-3bba8c1d-a474-44ec-b19b-738c401f1faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378232757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.1378232757
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.804820447
Short name T665
Test name
Test status
Simulation time 210932168 ps
CPU time 4.25 seconds
Started Jan 24 09:18:04 PM PST 24
Finished Jan 24 09:18:09 PM PST 24
Peak memory 243628 kb
Host smart-c98f768a-1990-4911-9fc1-a1e2df7dc04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804820447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.804820447
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.618576649
Short name T269
Test name
Test status
Simulation time 133187425 ps
CPU time 3.81 seconds
Started Jan 24 11:18:01 PM PST 24
Finished Jan 24 11:18:06 PM PST 24
Peak memory 244848 kb
Host smart-a9fe3fc9-6b1e-4ea2-9623-4b2f5462ff8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618576649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.618576649
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.2252098391
Short name T182
Test name
Test status
Simulation time 111436212 ps
CPU time 3.26 seconds
Started Jan 24 09:12:24 PM PST 24
Finished Jan 24 09:12:28 PM PST 24
Peak memory 243284 kb
Host smart-61a2ad6e-9aa5-4b44-890a-217e90d9e1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252098391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.2252098391
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.1085735442
Short name T240
Test name
Test status
Simulation time 197284037 ps
CPU time 4.62 seconds
Started Jan 24 09:12:23 PM PST 24
Finished Jan 24 09:12:28 PM PST 24
Peak memory 244792 kb
Host smart-b3357fbc-e266-467a-8a37-28965f8defc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085735442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.1085735442
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.2703925978
Short name T639
Test name
Test status
Simulation time 297588801 ps
CPU time 4.96 seconds
Started Jan 24 09:12:24 PM PST 24
Finished Jan 24 09:12:30 PM PST 24
Peak memory 245404 kb
Host smart-d876e209-517d-4106-9d08-f2c68a4c879d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703925978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.2703925978
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.1986368963
Short name T509
Test name
Test status
Simulation time 127693139 ps
CPU time 1.94 seconds
Started Jan 24 08:57:52 PM PST 24
Finished Jan 24 08:57:57 PM PST 24
Peak memory 239960 kb
Host smart-195816c2-be67-459e-aefb-b1689d9f9018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986368963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.1986368963
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.338423941
Short name T511
Test name
Test status
Simulation time 434098845 ps
CPU time 4.81 seconds
Started Jan 24 08:57:39 PM PST 24
Finished Jan 24 08:57:47 PM PST 24
Peak memory 243420 kb
Host smart-45434fdf-7c16-44be-90a0-638ce54b5ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338423941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.338423941
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.3166822266
Short name T566
Test name
Test status
Simulation time 442382275 ps
CPU time 8.66 seconds
Started Jan 24 08:57:35 PM PST 24
Finished Jan 24 08:57:45 PM PST 24
Peak memory 244992 kb
Host smart-50bcdc54-75d7-4f6f-b642-793718272eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166822266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.3166822266
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.912614519
Short name T217
Test name
Test status
Simulation time 320683736 ps
CPU time 8.13 seconds
Started Jan 24 08:57:38 PM PST 24
Finished Jan 24 08:57:50 PM PST 24
Peak memory 239624 kb
Host smart-f3470c5e-5d8d-4546-be26-e664ddbfc815
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=912614519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.912614519
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.1967847296
Short name T500
Test name
Test status
Simulation time 283996137 ps
CPU time 4.07 seconds
Started Jan 24 09:12:38 PM PST 24
Finished Jan 24 09:12:43 PM PST 24
Peak memory 244800 kb
Host smart-56f15a80-9a55-449a-b80c-7c3cbffd8645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967847296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.1967847296
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.4128239706
Short name T156
Test name
Test status
Simulation time 1798682391 ps
CPU time 11.88 seconds
Started Jan 24 09:12:41 PM PST 24
Finished Jan 24 09:12:54 PM PST 24
Peak memory 247680 kb
Host smart-5bd712c1-29fa-4ee6-9ff9-49525277aaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128239706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.4128239706
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.2927894055
Short name T610
Test name
Test status
Simulation time 447380147 ps
CPU time 4.66 seconds
Started Jan 24 09:12:38 PM PST 24
Finished Jan 24 09:12:43 PM PST 24
Peak memory 239472 kb
Host smart-fdbe9100-7eaf-4b44-b584-a924e3f84112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927894055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.2927894055
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.2673296388
Short name T716
Test name
Test status
Simulation time 152328479 ps
CPU time 4.22 seconds
Started Jan 24 09:12:50 PM PST 24
Finished Jan 24 09:12:56 PM PST 24
Peak memory 239480 kb
Host smart-bfbe731e-22c0-4935-a0cf-a96cb151c70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673296388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.2673296388
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.3122139762
Short name T330
Test name
Test status
Simulation time 386158474 ps
CPU time 9.03 seconds
Started Jan 24 09:12:39 PM PST 24
Finished Jan 24 09:12:49 PM PST 24
Peak memory 246784 kb
Host smart-f98986f9-1577-4fe3-bcc9-71136e3d60c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122139762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.3122139762
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.188895919
Short name T693
Test name
Test status
Simulation time 2104337227 ps
CPU time 5.91 seconds
Started Jan 24 09:12:38 PM PST 24
Finished Jan 24 09:12:45 PM PST 24
Peak memory 243636 kb
Host smart-958b23a6-4333-46e0-bb20-9210d81baf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188895919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.188895919
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.2754966907
Short name T154
Test name
Test status
Simulation time 330970530 ps
CPU time 5.38 seconds
Started Jan 24 09:12:50 PM PST 24
Finished Jan 24 09:12:57 PM PST 24
Peak memory 243744 kb
Host smart-7079c42a-c542-4f75-8ed2-7c6148178cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754966907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.2754966907
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.3428805593
Short name T559
Test name
Test status
Simulation time 1990074267 ps
CPU time 6.01 seconds
Started Jan 24 09:12:50 PM PST 24
Finished Jan 24 09:12:58 PM PST 24
Peak memory 243304 kb
Host smart-feecfec0-2387-47e4-9d16-1ae09c1fa7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428805593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.3428805593
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.1514915268
Short name T499
Test name
Test status
Simulation time 148052310 ps
CPU time 3.99 seconds
Started Jan 24 09:12:37 PM PST 24
Finished Jan 24 09:12:42 PM PST 24
Peak memory 244136 kb
Host smart-8b96633c-ebfe-4d0a-833a-e7f38127a441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514915268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.1514915268
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.337845958
Short name T545
Test name
Test status
Simulation time 213073885 ps
CPU time 6.15 seconds
Started Jan 24 10:10:28 PM PST 24
Finished Jan 24 10:10:38 PM PST 24
Peak memory 245448 kb
Host smart-330bd72f-69e3-4cbf-9738-2b6423d2bad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337845958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.337845958
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.711418440
Short name T536
Test name
Test status
Simulation time 207483811 ps
CPU time 4.34 seconds
Started Jan 24 09:13:15 PM PST 24
Finished Jan 24 09:13:20 PM PST 24
Peak memory 243384 kb
Host smart-8fe57f69-1ed2-41ad-ae8b-ad5862c3c0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711418440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.711418440
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.2527761980
Short name T263
Test name
Test status
Simulation time 334078853 ps
CPU time 4 seconds
Started Jan 24 11:46:16 PM PST 24
Finished Jan 24 11:46:21 PM PST 24
Peak memory 243396 kb
Host smart-a54b1268-37bf-45cb-b829-068c7be166dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527761980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.2527761980
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.1670705464
Short name T686
Test name
Test status
Simulation time 619289843 ps
CPU time 8.72 seconds
Started Jan 24 09:44:27 PM PST 24
Finished Jan 24 09:44:37 PM PST 24
Peak memory 245156 kb
Host smart-b9522620-b285-4960-bf63-b2f678e263ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670705464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.1670705464
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.561365301
Short name T497
Test name
Test status
Simulation time 57988292 ps
CPU time 1.68 seconds
Started Jan 24 09:35:46 PM PST 24
Finished Jan 24 09:35:48 PM PST 24
Peak memory 239336 kb
Host smart-e58f83c3-8e91-4168-8a69-419ef7a1d30c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561365301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.561365301
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.2088629432
Short name T173
Test name
Test status
Simulation time 496495482 ps
CPU time 4.71 seconds
Started Jan 24 08:57:53 PM PST 24
Finished Jan 24 08:58:02 PM PST 24
Peak memory 243276 kb
Host smart-9f9516c2-3098-4aa6-878a-ed1a8da2604e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088629432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.2088629432
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.4188802239
Short name T9
Test name
Test status
Simulation time 1012338748 ps
CPU time 7.66 seconds
Started Jan 24 11:08:07 PM PST 24
Finished Jan 24 11:08:15 PM PST 24
Peak memory 245008 kb
Host smart-0c231f9d-a227-46c3-882c-c5c108176b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188802239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.4188802239
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.2258867829
Short name T214
Test name
Test status
Simulation time 385527158 ps
CPU time 5.18 seconds
Started Jan 24 08:57:53 PM PST 24
Finished Jan 24 08:58:01 PM PST 24
Peak memory 239592 kb
Host smart-ef4be3ca-1d8c-4a47-b0fe-043519dcc373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258867829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.2258867829
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.1594510493
Short name T558
Test name
Test status
Simulation time 370728155 ps
CPU time 4.39 seconds
Started Jan 24 09:53:26 PM PST 24
Finished Jan 24 09:53:31 PM PST 24
Peak memory 246476 kb
Host smart-9384e622-0ac8-4353-a639-4c3222bc96ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594510493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.1594510493
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.2934584575
Short name T169
Test name
Test status
Simulation time 124574079 ps
CPU time 3.06 seconds
Started Jan 24 09:13:06 PM PST 24
Finished Jan 24 09:13:15 PM PST 24
Peak memory 242828 kb
Host smart-dd89526f-893e-407b-b2fc-1b1715ca549f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934584575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.2934584575
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.2498898504
Short name T200
Test name
Test status
Simulation time 118789429 ps
CPU time 3.85 seconds
Started Jan 24 09:13:06 PM PST 24
Finished Jan 24 09:13:15 PM PST 24
Peak memory 245160 kb
Host smart-f5238058-5868-4312-9c6c-54abc82d7dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498898504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.2498898504
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.628087406
Short name T482
Test name
Test status
Simulation time 145636917 ps
CPU time 3.63 seconds
Started Jan 24 09:47:47 PM PST 24
Finished Jan 24 09:47:51 PM PST 24
Peak memory 243232 kb
Host smart-f2d7478a-652b-4ab2-90db-e235f8579d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628087406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.628087406
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.748530765
Short name T474
Test name
Test status
Simulation time 223686109 ps
CPU time 5.14 seconds
Started Jan 24 09:13:05 PM PST 24
Finished Jan 24 09:13:17 PM PST 24
Peak memory 243372 kb
Host smart-ba1ea3c5-b502-413d-9514-8f86d27f5a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748530765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.748530765
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.1974245402
Short name T473
Test name
Test status
Simulation time 331610449 ps
CPU time 3.9 seconds
Started Jan 24 09:13:07 PM PST 24
Finished Jan 24 09:13:15 PM PST 24
Peak memory 239548 kb
Host smart-24e7660d-bdde-42a4-bbb4-dd85729fc890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974245402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.1974245402
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.1647907852
Short name T342
Test name
Test status
Simulation time 125518398 ps
CPU time 3.8 seconds
Started Jan 24 09:13:47 PM PST 24
Finished Jan 24 09:13:52 PM PST 24
Peak memory 239444 kb
Host smart-7c972fb6-5907-4d72-afb2-17867fdeb25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647907852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.1647907852
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.1949494993
Short name T603
Test name
Test status
Simulation time 2284510096 ps
CPU time 4.5 seconds
Started Jan 24 09:13:42 PM PST 24
Finished Jan 24 09:13:47 PM PST 24
Peak memory 239524 kb
Host smart-8d203cb0-f76e-4c4d-82d6-eff17d61355e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949494993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.1949494993
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.3890724763
Short name T627
Test name
Test status
Simulation time 227079816 ps
CPU time 4.39 seconds
Started Jan 24 09:13:41 PM PST 24
Finished Jan 24 09:13:47 PM PST 24
Peak memory 243596 kb
Host smart-4400ca7a-2034-4966-b1b8-7c19db800311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890724763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.3890724763
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.997805976
Short name T644
Test name
Test status
Simulation time 1801152492 ps
CPU time 7.7 seconds
Started Jan 24 09:13:45 PM PST 24
Finished Jan 24 09:13:54 PM PST 24
Peak memory 245316 kb
Host smart-08f9e136-f131-424f-b533-cc5b6dc1ef55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997805976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.997805976
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.4226929861
Short name T647
Test name
Test status
Simulation time 141760431 ps
CPU time 1.99 seconds
Started Jan 24 08:58:07 PM PST 24
Finished Jan 24 08:58:15 PM PST 24
Peak memory 239896 kb
Host smart-8b90f650-dedb-45fb-a871-b922e60cceb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226929861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.4226929861
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.2413162596
Short name T185
Test name
Test status
Simulation time 142470712 ps
CPU time 4.12 seconds
Started Jan 24 08:57:53 PM PST 24
Finished Jan 24 08:58:00 PM PST 24
Peak memory 243444 kb
Host smart-4aad3812-01dc-4094-8ba4-c418e1227bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413162596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.2413162596
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.2432461833
Short name T588
Test name
Test status
Simulation time 1052321544 ps
CPU time 8.74 seconds
Started Jan 24 08:57:51 PM PST 24
Finished Jan 24 08:58:03 PM PST 24
Peak memory 239632 kb
Host smart-043ef9d9-3132-4825-a517-0ca4f816278d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2432461833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.2432461833
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.2544370964
Short name T349
Test name
Test status
Simulation time 355983679 ps
CPU time 5.14 seconds
Started Jan 24 09:43:14 PM PST 24
Finished Jan 24 09:43:20 PM PST 24
Peak memory 239668 kb
Host smart-9eb34dde-35c0-4467-b722-29c765580b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544370964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.2544370964
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.446719967
Short name T436
Test name
Test status
Simulation time 435677634 ps
CPU time 3.89 seconds
Started Jan 24 09:13:46 PM PST 24
Finished Jan 24 09:13:51 PM PST 24
Peak memory 239448 kb
Host smart-f26615df-9a7e-4b64-84f0-0404c7d2c7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446719967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.446719967
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.2927068870
Short name T324
Test name
Test status
Simulation time 6222547084 ps
CPU time 12.6 seconds
Started Jan 24 09:13:41 PM PST 24
Finished Jan 24 09:13:55 PM PST 24
Peak memory 247500 kb
Host smart-4c134374-6024-4886-89ae-262776d45a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927068870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.2927068870
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.2843241005
Short name T455
Test name
Test status
Simulation time 221521975 ps
CPU time 3.85 seconds
Started Jan 24 09:13:45 PM PST 24
Finished Jan 24 09:13:51 PM PST 24
Peak memory 243016 kb
Host smart-a475c9c4-5eef-4fe2-9002-44a8fb9f2fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843241005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.2843241005
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.3316586855
Short name T490
Test name
Test status
Simulation time 1836635981 ps
CPU time 4.39 seconds
Started Jan 24 09:13:41 PM PST 24
Finished Jan 24 09:13:46 PM PST 24
Peak memory 243752 kb
Host smart-4a22aeb7-356d-451e-a632-829ead6144cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316586855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.3316586855
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.2443596595
Short name T193
Test name
Test status
Simulation time 3353013438 ps
CPU time 14.69 seconds
Started Jan 24 09:13:45 PM PST 24
Finished Jan 24 09:14:01 PM PST 24
Peak memory 246668 kb
Host smart-5c64775d-e694-4fef-9de6-69c07a83f8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443596595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.2443596595
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.731883547
Short name T642
Test name
Test status
Simulation time 294295793 ps
CPU time 4.09 seconds
Started Jan 24 09:13:47 PM PST 24
Finished Jan 24 09:13:52 PM PST 24
Peak memory 243504 kb
Host smart-dd6b9ce0-5636-4a26-a364-f766dc43f527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731883547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.731883547
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.1174376450
Short name T76
Test name
Test status
Simulation time 215492143 ps
CPU time 3.68 seconds
Started Jan 24 11:40:49 PM PST 24
Finished Jan 24 11:40:54 PM PST 24
Peak memory 239564 kb
Host smart-c16ba2bb-8aee-41df-9562-048668413780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174376450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.1174376450
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.4254720722
Short name T195
Test name
Test status
Simulation time 1007853158 ps
CPU time 6.74 seconds
Started Jan 24 09:13:40 PM PST 24
Finished Jan 24 09:13:48 PM PST 24
Peak memory 245548 kb
Host smart-c711782c-56a4-4dd5-9801-1678311a9891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254720722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.4254720722
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.4181199774
Short name T37
Test name
Test status
Simulation time 526590578 ps
CPU time 4.44 seconds
Started Jan 24 09:13:39 PM PST 24
Finished Jan 24 09:13:45 PM PST 24
Peak memory 239572 kb
Host smart-6ccdf0cf-1a2d-4d2c-be86-e4ed5f06b06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181199774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.4181199774
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.1120185871
Short name T281
Test name
Test status
Simulation time 235175315 ps
CPU time 2.17 seconds
Started Jan 24 08:58:25 PM PST 24
Finished Jan 24 08:58:28 PM PST 24
Peak memory 239136 kb
Host smart-621464b7-8913-4c8c-bac7-c5b52dac9a98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120185871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.1120185871
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.1772038663
Short name T549
Test name
Test status
Simulation time 421043996 ps
CPU time 3.85 seconds
Started Jan 24 09:15:31 PM PST 24
Finished Jan 24 09:15:36 PM PST 24
Peak memory 239684 kb
Host smart-3d63eb7f-7434-4d83-8701-f49adda330c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1772038663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.1772038663
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.2290355786
Short name T547
Test name
Test status
Simulation time 179312413 ps
CPU time 4.9 seconds
Started Jan 24 08:58:06 PM PST 24
Finished Jan 24 08:58:15 PM PST 24
Peak memory 239528 kb
Host smart-ba3cb77a-fe1f-4e5e-8e0e-125ce0436e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290355786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.2290355786
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.2366645762
Short name T561
Test name
Test status
Simulation time 126297552 ps
CPU time 3.82 seconds
Started Jan 24 09:13:42 PM PST 24
Finished Jan 24 09:13:47 PM PST 24
Peak memory 243340 kb
Host smart-6459ee0c-6286-45ad-abf4-d9b671057fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366645762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.2366645762
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.2098776399
Short name T203
Test name
Test status
Simulation time 264554885 ps
CPU time 4.28 seconds
Started Jan 24 09:13:46 PM PST 24
Finished Jan 24 09:13:51 PM PST 24
Peak memory 239444 kb
Host smart-7fed20df-7eac-48b4-bd59-aa3cf9646ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098776399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.2098776399
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.3285717236
Short name T661
Test name
Test status
Simulation time 1869502876 ps
CPU time 5.18 seconds
Started Jan 24 09:33:17 PM PST 24
Finished Jan 24 09:33:23 PM PST 24
Peak memory 243400 kb
Host smart-a3afbd99-f565-4a16-9431-9e8684444f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285717236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.3285717236
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.2287722493
Short name T616
Test name
Test status
Simulation time 212730536 ps
CPU time 5.42 seconds
Started Jan 24 09:14:07 PM PST 24
Finished Jan 24 09:14:14 PM PST 24
Peak memory 244964 kb
Host smart-55115333-6edd-4c96-829d-8c3147a757a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287722493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.2287722493
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.1179603418
Short name T631
Test name
Test status
Simulation time 264000148 ps
CPU time 4.79 seconds
Started Jan 24 09:14:08 PM PST 24
Finished Jan 24 09:14:14 PM PST 24
Peak memory 239524 kb
Host smart-9a01d16a-f15b-46c6-bb89-bb57045c1ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179603418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.1179603418
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.245390466
Short name T64
Test name
Test status
Simulation time 123742314 ps
CPU time 3.14 seconds
Started Jan 24 09:14:06 PM PST 24
Finished Jan 24 09:14:10 PM PST 24
Peak memory 239564 kb
Host smart-4dc8c6f2-61e7-4718-857b-24ef3525804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245390466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.245390466
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.1214213382
Short name T527
Test name
Test status
Simulation time 467384358 ps
CPU time 3.94 seconds
Started Jan 24 09:14:09 PM PST 24
Finished Jan 24 09:14:15 PM PST 24
Peak memory 239484 kb
Host smart-98c0c5e4-fcfb-4ef3-b128-fc0750b1b01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214213382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.1214213382
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.3576605607
Short name T155
Test name
Test status
Simulation time 468950863 ps
CPU time 11.58 seconds
Started Jan 24 09:14:04 PM PST 24
Finished Jan 24 09:14:17 PM PST 24
Peak memory 246972 kb
Host smart-9b8c53da-7873-43d7-9401-9963faddb2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576605607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.3576605607
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.87098040
Short name T690
Test name
Test status
Simulation time 192136053 ps
CPU time 4.07 seconds
Started Jan 24 09:14:08 PM PST 24
Finished Jan 24 09:14:13 PM PST 24
Peak memory 243464 kb
Host smart-4ac7ef79-27d9-4eb2-89fe-95f7279d9e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87098040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.87098040
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.3270685191
Short name T465
Test name
Test status
Simulation time 337580533 ps
CPU time 5.53 seconds
Started Jan 24 09:14:02 PM PST 24
Finished Jan 24 09:14:08 PM PST 24
Peak memory 243852 kb
Host smart-5f12e936-2165-42db-b7d5-4d1c4dd5a740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270685191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.3270685191
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.838126557
Short name T516
Test name
Test status
Simulation time 640079228 ps
CPU time 3.98 seconds
Started Jan 24 09:14:05 PM PST 24
Finished Jan 24 09:14:10 PM PST 24
Peak memory 243608 kb
Host smart-e11dfc01-06ab-4834-94ab-5ccfd308c490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838126557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.838126557
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.3204298148
Short name T568
Test name
Test status
Simulation time 406352750 ps
CPU time 3.76 seconds
Started Jan 24 09:14:06 PM PST 24
Finished Jan 24 09:14:11 PM PST 24
Peak memory 239492 kb
Host smart-4af0a43a-dad7-4114-a5b4-0e0720864d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204298148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.3204298148
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.2205316687
Short name T607
Test name
Test status
Simulation time 148420869 ps
CPU time 4.15 seconds
Started Jan 24 09:14:03 PM PST 24
Finished Jan 24 09:14:07 PM PST 24
Peak memory 239528 kb
Host smart-604956e5-d8d8-49b7-b529-c890c3e366f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205316687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.2205316687
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.155120394
Short name T449
Test name
Test status
Simulation time 223674266 ps
CPU time 1.89 seconds
Started Jan 24 08:58:27 PM PST 24
Finished Jan 24 08:58:31 PM PST 24
Peak memory 239652 kb
Host smart-0865f84c-5adb-4d0a-b555-3ef05fdfa9ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155120394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.155120394
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.882695382
Short name T247
Test name
Test status
Simulation time 196546774 ps
CPU time 4.74 seconds
Started Jan 24 09:32:02 PM PST 24
Finished Jan 24 09:32:09 PM PST 24
Peak memory 243464 kb
Host smart-7f8d2dce-84a6-4d8e-8e7e-600122387679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882695382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.882695382
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.3731802232
Short name T230
Test name
Test status
Simulation time 662469817 ps
CPU time 5.63 seconds
Started Jan 24 08:58:18 PM PST 24
Finished Jan 24 08:58:26 PM PST 24
Peak memory 246308 kb
Host smart-7aa26d49-f8bf-495e-8c58-9c40fc737c49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3731802232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.3731802232
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.3118362688
Short name T706
Test name
Test status
Simulation time 2359501356 ps
CPU time 7.03 seconds
Started Jan 24 08:58:16 PM PST 24
Finished Jan 24 08:58:24 PM PST 24
Peak memory 239724 kb
Host smart-33b36f6f-bf16-4e5f-b816-f05bb4f388ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118362688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.3118362688
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.936114053
Short name T691
Test name
Test status
Simulation time 120492200 ps
CPU time 3.61 seconds
Started Jan 24 09:14:21 PM PST 24
Finished Jan 24 09:14:25 PM PST 24
Peak memory 239476 kb
Host smart-f0e5b337-cc3e-4dbd-baf1-1e27c3119193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936114053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.936114053
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.2796958266
Short name T486
Test name
Test status
Simulation time 166892909 ps
CPU time 4.04 seconds
Started Jan 24 09:14:32 PM PST 24
Finished Jan 24 09:14:37 PM PST 24
Peak memory 243484 kb
Host smart-c4e88b8a-fe41-4135-b912-ba0451943783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796958266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.2796958266
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.568556712
Short name T517
Test name
Test status
Simulation time 888612086 ps
CPU time 13.47 seconds
Started Jan 24 10:08:57 PM PST 24
Finished Jan 24 10:09:11 PM PST 24
Peak memory 247028 kb
Host smart-c2fbc505-d632-4eb1-8e64-f5c9a3760a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568556712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.568556712
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.2136441195
Short name T533
Test name
Test status
Simulation time 180330888 ps
CPU time 4.47 seconds
Started Jan 24 09:51:27 PM PST 24
Finished Jan 24 09:51:34 PM PST 24
Peak memory 243580 kb
Host smart-b3053d6b-5c0e-4224-863f-11abdf54f3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136441195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.2136441195
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.3351803820
Short name T612
Test name
Test status
Simulation time 154576877 ps
CPU time 4.05 seconds
Started Jan 24 09:14:28 PM PST 24
Finished Jan 24 09:14:33 PM PST 24
Peak memory 239476 kb
Host smart-c58f1cac-3007-42b9-90a5-bc3fe66289b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351803820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.3351803820
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.2318685674
Short name T445
Test name
Test status
Simulation time 600911107 ps
CPU time 4.34 seconds
Started Jan 24 09:14:23 PM PST 24
Finished Jan 24 09:14:29 PM PST 24
Peak memory 239528 kb
Host smart-e951453a-a865-4209-b1b2-48cfe0d9535d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318685674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.2318685674
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.4215998311
Short name T648
Test name
Test status
Simulation time 245380564 ps
CPU time 4.4 seconds
Started Jan 24 09:32:59 PM PST 24
Finished Jan 24 09:33:05 PM PST 24
Peak memory 244164 kb
Host smart-668cf6fb-8dcc-45bf-8ce9-7c5e0a3a9e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215998311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.4215998311
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.3262031254
Short name T34
Test name
Test status
Simulation time 238075334 ps
CPU time 3.36 seconds
Started Jan 24 11:15:29 PM PST 24
Finished Jan 24 11:15:35 PM PST 24
Peak memory 243688 kb
Host smart-4e17a5ff-fadb-4adf-89e5-9b3e122bb6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262031254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.3262031254
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.100672692
Short name T339
Test name
Test status
Simulation time 280399399 ps
CPU time 3.99 seconds
Started Jan 24 09:14:33 PM PST 24
Finished Jan 24 09:14:37 PM PST 24
Peak memory 242876 kb
Host smart-d41f23a4-5026-4f19-a00b-1b03a6170f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100672692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.100672692
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.4077584700
Short name T22
Test name
Test status
Simulation time 173037632 ps
CPU time 4.3 seconds
Started Jan 24 10:51:21 PM PST 24
Finished Jan 24 10:51:26 PM PST 24
Peak memory 239620 kb
Host smart-9469b873-1ede-468c-a5d0-fe1e478f4d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077584700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.4077584700
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.92107989
Short name T463
Test name
Test status
Simulation time 281257037 ps
CPU time 3.77 seconds
Started Jan 24 09:14:29 PM PST 24
Finished Jan 24 09:14:34 PM PST 24
Peak memory 239420 kb
Host smart-ab954a16-3347-4762-b97a-5da2a4856cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92107989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.92107989
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.3326402881
Short name T689
Test name
Test status
Simulation time 129906040 ps
CPU time 4.16 seconds
Started Jan 24 10:34:42 PM PST 24
Finished Jan 24 10:34:53 PM PST 24
Peak memory 239560 kb
Host smart-d864c411-b07b-4b8f-9bc2-559ab76b6418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326402881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.3326402881
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.1580026883
Short name T525
Test name
Test status
Simulation time 265358200 ps
CPU time 2.21 seconds
Started Jan 24 08:54:04 PM PST 24
Finished Jan 24 08:54:07 PM PST 24
Peak memory 239376 kb
Host smart-622cf986-78fc-4e77-8308-4490875f070a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580026883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.1580026883
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.777543096
Short name T205
Test name
Test status
Simulation time 388839717 ps
CPU time 3.26 seconds
Started Jan 24 08:53:58 PM PST 24
Finished Jan 24 08:54:02 PM PST 24
Peak memory 242896 kb
Host smart-fe2f245b-15df-4839-8f2c-ee1d0a44b941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777543096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.777543096
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.521914482
Short name T69
Test name
Test status
Simulation time 559201956 ps
CPU time 6.23 seconds
Started Jan 24 09:08:19 PM PST 24
Finished Jan 24 09:08:27 PM PST 24
Peak memory 239588 kb
Host smart-55e081bb-1d20-41f8-8946-51a4752e3bd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=521914482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.521914482
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.2318919412
Short name T103
Test name
Test status
Simulation time 3377228357 ps
CPU time 6.78 seconds
Started Jan 24 08:53:58 PM PST 24
Finished Jan 24 08:54:05 PM PST 24
Peak memory 239788 kb
Host smart-eaca1e3e-448f-48a3-a596-daa065b7c6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318919412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.2318919412
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.1212064856
Short name T491
Test name
Test status
Simulation time 312862524 ps
CPU time 4.17 seconds
Started Jan 24 08:58:50 PM PST 24
Finished Jan 24 08:58:57 PM PST 24
Peak memory 244668 kb
Host smart-63f71cbe-ab0c-4098-99c5-a3a525270eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212064856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.1212064856
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.2236430274
Short name T322
Test name
Test status
Simulation time 600116806 ps
CPU time 3.51 seconds
Started Jan 24 08:58:42 PM PST 24
Finished Jan 24 08:58:50 PM PST 24
Peak memory 247756 kb
Host smart-0286490a-f2d3-49ce-b74e-ccc75a728d72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2236430274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.2236430274
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.2795602160
Short name T643
Test name
Test status
Simulation time 431841137 ps
CPU time 3.74 seconds
Started Jan 24 09:14:53 PM PST 24
Finished Jan 24 09:14:57 PM PST 24
Peak memory 243344 kb
Host smart-c3aad947-e0f4-4be5-8fcb-2280038a7cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795602160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.2795602160
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.1609461681
Short name T164
Test name
Test status
Simulation time 133829667 ps
CPU time 3.94 seconds
Started Jan 24 09:15:01 PM PST 24
Finished Jan 24 09:15:06 PM PST 24
Peak memory 243648 kb
Host smart-c5c9a8d0-537c-4287-987d-148da6549608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609461681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.1609461681
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.3048430556
Short name T444
Test name
Test status
Simulation time 165692401 ps
CPU time 3.82 seconds
Started Jan 24 09:14:50 PM PST 24
Finished Jan 24 09:14:55 PM PST 24
Peak memory 243676 kb
Host smart-69eba054-895c-4b83-8869-e29e7a4de633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048430556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.3048430556
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.3668213026
Short name T186
Test name
Test status
Simulation time 360995358 ps
CPU time 3.62 seconds
Started Jan 24 09:14:49 PM PST 24
Finished Jan 24 09:14:55 PM PST 24
Peak memory 243256 kb
Host smart-3421099f-44f7-4dea-bf9a-f06ce5764d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668213026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.3668213026
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.2891655566
Short name T707
Test name
Test status
Simulation time 474538503 ps
CPU time 4.17 seconds
Started Jan 24 09:14:53 PM PST 24
Finished Jan 24 09:14:58 PM PST 24
Peak memory 239524 kb
Host smart-efe29687-49a4-4add-a422-5233378e9e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891655566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.2891655566
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.1582563483
Short name T167
Test name
Test status
Simulation time 183812257 ps
CPU time 4.3 seconds
Started Jan 24 09:14:49 PM PST 24
Finished Jan 24 09:14:55 PM PST 24
Peak memory 243336 kb
Host smart-a7ba20cd-09b6-4bbc-8bd0-16615dbf88c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582563483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.1582563483
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.119237881
Short name T61
Test name
Test status
Simulation time 1941211602 ps
CPU time 3.23 seconds
Started Jan 24 09:14:53 PM PST 24
Finished Jan 24 09:14:58 PM PST 24
Peak memory 242972 kb
Host smart-a68e2b54-b7d4-408b-8ac5-358c2a89c972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119237881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.119237881
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.878734662
Short name T615
Test name
Test status
Simulation time 2583882928 ps
CPU time 8.39 seconds
Started Jan 24 09:14:50 PM PST 24
Finished Jan 24 09:15:00 PM PST 24
Peak memory 239672 kb
Host smart-b782493d-b3c1-45ff-a311-29f312007a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878734662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.878734662
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.3658396909
Short name T632
Test name
Test status
Simulation time 2057519096 ps
CPU time 5.54 seconds
Started Jan 24 09:15:40 PM PST 24
Finished Jan 24 09:15:47 PM PST 24
Peak memory 242940 kb
Host smart-57e9aab2-0997-446c-9308-0c35583b819b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658396909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.3658396909
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.3205160105
Short name T579
Test name
Test status
Simulation time 111675688 ps
CPU time 1.87 seconds
Started Jan 24 08:59:03 PM PST 24
Finished Jan 24 08:59:06 PM PST 24
Peak memory 239780 kb
Host smart-27491a80-5c1f-46d2-87ab-883581fe1ad3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205160105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.3205160105
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.359758644
Short name T448
Test name
Test status
Simulation time 125829341 ps
CPU time 4.9 seconds
Started Jan 24 08:58:58 PM PST 24
Finished Jan 24 08:59:04 PM PST 24
Peak memory 239548 kb
Host smart-0ad868ab-1df0-4344-b5dc-3598cfa019bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=359758644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.359758644
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.2216656393
Short name T597
Test name
Test status
Simulation time 130511503 ps
CPU time 3.81 seconds
Started Jan 24 09:15:38 PM PST 24
Finished Jan 24 09:15:43 PM PST 24
Peak memory 239508 kb
Host smart-170e6307-b3a9-4ed8-b7c7-ce82ea19414e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216656393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.2216656393
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.1177050492
Short name T53
Test name
Test status
Simulation time 235736195 ps
CPU time 3.51 seconds
Started Jan 24 09:15:36 PM PST 24
Finished Jan 24 09:15:41 PM PST 24
Peak memory 239464 kb
Host smart-7e124a5c-0893-4e30-9819-e2a7d740dc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177050492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.1177050492
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.2951137043
Short name T33
Test name
Test status
Simulation time 120022534 ps
CPU time 4.12 seconds
Started Jan 24 09:15:43 PM PST 24
Finished Jan 24 09:15:49 PM PST 24
Peak memory 243244 kb
Host smart-73bbb608-daaf-4120-a052-3a4713b06fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951137043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.2951137043
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.418848234
Short name T268
Test name
Test status
Simulation time 599227738 ps
CPU time 5.03 seconds
Started Jan 24 09:15:40 PM PST 24
Finished Jan 24 09:15:48 PM PST 24
Peak memory 243204 kb
Host smart-82699ca4-4107-45e6-9700-e8fcf0acee44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418848234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.418848234
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.786091426
Short name T39
Test name
Test status
Simulation time 185165327 ps
CPU time 3.14 seconds
Started Jan 24 09:15:42 PM PST 24
Finished Jan 24 09:15:47 PM PST 24
Peak memory 242676 kb
Host smart-850b1a9c-5714-4091-9d17-2702e2f4d16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786091426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.786091426
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.1072073227
Short name T698
Test name
Test status
Simulation time 265375329 ps
CPU time 4.12 seconds
Started Jan 24 09:15:39 PM PST 24
Finished Jan 24 09:15:44 PM PST 24
Peak memory 243140 kb
Host smart-25b9c68f-ac7e-472b-877e-ac8ae6da888a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072073227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.1072073227
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.84090383
Short name T652
Test name
Test status
Simulation time 2676906498 ps
CPU time 4.99 seconds
Started Jan 24 09:15:38 PM PST 24
Finished Jan 24 09:15:44 PM PST 24
Peak memory 239600 kb
Host smart-7f56e49d-973c-423e-92ae-2430b44070b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84090383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.84090383
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.1724109980
Short name T590
Test name
Test status
Simulation time 138416260 ps
CPU time 3.46 seconds
Started Jan 24 09:15:36 PM PST 24
Finished Jan 24 09:15:41 PM PST 24
Peak memory 242564 kb
Host smart-d2120f05-757b-4bae-8c50-91fb35bfd243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724109980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.1724109980
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.2141288975
Short name T634
Test name
Test status
Simulation time 181616236 ps
CPU time 1.73 seconds
Started Jan 24 08:59:14 PM PST 24
Finished Jan 24 08:59:17 PM PST 24
Peak memory 239748 kb
Host smart-e64d0098-4d72-4fd6-b5a6-0f1142fe0dae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141288975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.2141288975
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.345503520
Short name T441
Test name
Test status
Simulation time 117184579 ps
CPU time 4.35 seconds
Started Jan 24 08:58:57 PM PST 24
Finished Jan 24 08:59:03 PM PST 24
Peak memory 244612 kb
Host smart-14d3255a-22df-4ee8-89b6-f7b6885204ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345503520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.345503520
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.1714029776
Short name T563
Test name
Test status
Simulation time 538538784 ps
CPU time 4.53 seconds
Started Jan 24 08:59:12 PM PST 24
Finished Jan 24 08:59:18 PM PST 24
Peak memory 239600 kb
Host smart-c47df293-432e-413b-b272-7af66dd8a08f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1714029776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.1714029776
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.1686560941
Short name T495
Test name
Test status
Simulation time 323077779 ps
CPU time 3 seconds
Started Jan 24 08:58:59 PM PST 24
Finished Jan 24 08:59:03 PM PST 24
Peak memory 239668 kb
Host smart-bc29177e-cb73-45d3-a330-f23c577f6b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686560941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.1686560941
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.2275200313
Short name T713
Test name
Test status
Simulation time 205688918 ps
CPU time 3.78 seconds
Started Jan 24 09:15:41 PM PST 24
Finished Jan 24 09:15:47 PM PST 24
Peak memory 243524 kb
Host smart-0557d2a5-7fd8-4ebc-9fd7-cc966a6a80ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275200313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.2275200313
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.543184791
Short name T79
Test name
Test status
Simulation time 132573121 ps
CPU time 3.46 seconds
Started Jan 24 09:15:37 PM PST 24
Finished Jan 24 09:15:42 PM PST 24
Peak memory 243412 kb
Host smart-4ac755e0-213e-437c-bb5f-265cfcdd0392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543184791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.543184791
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.263933823
Short name T513
Test name
Test status
Simulation time 429637709 ps
CPU time 4.2 seconds
Started Jan 24 09:15:36 PM PST 24
Finished Jan 24 09:15:42 PM PST 24
Peak memory 239520 kb
Host smart-0014cc31-b395-4402-8ba1-3ad6d84b4462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263933823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.263933823
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.3348043144
Short name T650
Test name
Test status
Simulation time 2720844167 ps
CPU time 6.01 seconds
Started Jan 24 09:15:41 PM PST 24
Finished Jan 24 09:15:49 PM PST 24
Peak memory 239620 kb
Host smart-9d321fd1-04d0-4d8d-9998-8b4ea911b131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348043144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.3348043144
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.1940289207
Short name T695
Test name
Test status
Simulation time 458037734 ps
CPU time 3.1 seconds
Started Jan 24 09:15:36 PM PST 24
Finished Jan 24 09:15:40 PM PST 24
Peak memory 239520 kb
Host smart-f796d41b-1256-45a4-a18d-4b97c14eebae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940289207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.1940289207
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.2824748642
Short name T501
Test name
Test status
Simulation time 410291395 ps
CPU time 4.52 seconds
Started Jan 24 09:15:37 PM PST 24
Finished Jan 24 09:15:43 PM PST 24
Peak memory 244392 kb
Host smart-3ecc12bf-46f0-4235-a663-42c29a578b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824748642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.2824748642
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.4007307729
Short name T102
Test name
Test status
Simulation time 479696042 ps
CPU time 4.08 seconds
Started Jan 24 09:15:40 PM PST 24
Finished Jan 24 09:15:47 PM PST 24
Peak memory 239452 kb
Host smart-658688ef-9228-4d4b-a27f-0d437f117448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007307729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.4007307729
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.1600226047
Short name T453
Test name
Test status
Simulation time 2182054743 ps
CPU time 5.05 seconds
Started Jan 24 09:15:36 PM PST 24
Finished Jan 24 09:15:41 PM PST 24
Peak memory 243616 kb
Host smart-1f8ba8b8-afcf-45b8-bd22-489b193d30a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600226047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.1600226047
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.2703390021
Short name T31
Test name
Test status
Simulation time 298095509 ps
CPU time 3.83 seconds
Started Jan 24 09:19:17 PM PST 24
Finished Jan 24 09:19:25 PM PST 24
Peak memory 243392 kb
Host smart-ad20b466-48af-4494-a4f5-50ae61249c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703390021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.2703390021
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.682156465
Short name T681
Test name
Test status
Simulation time 290638383 ps
CPU time 3.75 seconds
Started Jan 24 09:15:08 PM PST 24
Finished Jan 24 09:15:13 PM PST 24
Peak memory 243076 kb
Host smart-3c6bcae7-20d9-4627-8e74-77fe02414348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682156465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.682156465
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.3223463836
Short name T656
Test name
Test status
Simulation time 840648271 ps
CPU time 5.01 seconds
Started Jan 24 08:59:31 PM PST 24
Finished Jan 24 08:59:37 PM PST 24
Peak memory 239312 kb
Host smart-f4e1627d-eefe-41c3-9756-1e1beedcf57e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223463836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.3223463836
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.2951784781
Short name T678
Test name
Test status
Simulation time 308280647 ps
CPU time 4.27 seconds
Started Jan 24 08:59:09 PM PST 24
Finished Jan 24 08:59:15 PM PST 24
Peak memory 244168 kb
Host smart-4ac6df0a-e279-4749-9722-9f76450dfc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951784781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.2951784781
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.1347582148
Short name T670
Test name
Test status
Simulation time 356527857 ps
CPU time 4.49 seconds
Started Jan 24 08:59:16 PM PST 24
Finished Jan 24 08:59:22 PM PST 24
Peak memory 239596 kb
Host smart-c160775c-7ad8-46b0-97b3-66541f841f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347582148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.1347582148
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.1093882086
Short name T658
Test name
Test status
Simulation time 265868730 ps
CPU time 3.05 seconds
Started Jan 24 08:59:32 PM PST 24
Finished Jan 24 08:59:35 PM PST 24
Peak memory 239624 kb
Host smart-910567ad-99d6-4eb0-932b-ab1696ba6eb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1093882086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.1093882086
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.2476163102
Short name T669
Test name
Test status
Simulation time 4238545480 ps
CPU time 11.9 seconds
Started Jan 24 08:59:12 PM PST 24
Finished Jan 24 08:59:24 PM PST 24
Peak memory 247892 kb
Host smart-ecf92363-598b-4f66-9e36-e93717c1ebc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476163102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.2476163102
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.784160786
Short name T351
Test name
Test status
Simulation time 349337875 ps
CPU time 4.39 seconds
Started Jan 24 09:15:43 PM PST 24
Finished Jan 24 09:15:49 PM PST 24
Peak memory 239320 kb
Host smart-ec28ab41-d5f6-4f12-b720-19fd3435f49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784160786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.784160786
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.1657020963
Short name T651
Test name
Test status
Simulation time 129554360 ps
CPU time 3.3 seconds
Started Jan 24 09:39:32 PM PST 24
Finished Jan 24 09:39:36 PM PST 24
Peak memory 239512 kb
Host smart-cd76094c-b711-4e9f-a421-7d2414a74291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657020963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.1657020963
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.2467553436
Short name T602
Test name
Test status
Simulation time 119816203 ps
CPU time 2.86 seconds
Started Jan 24 09:15:41 PM PST 24
Finished Jan 24 09:15:47 PM PST 24
Peak memory 244184 kb
Host smart-99746d1f-9652-4faa-a370-f822f4f8bdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467553436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.2467553436
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.1815826326
Short name T73
Test name
Test status
Simulation time 165189312 ps
CPU time 3.19 seconds
Started Jan 24 09:15:38 PM PST 24
Finished Jan 24 09:15:43 PM PST 24
Peak memory 242844 kb
Host smart-721e433a-1a10-40a0-9461-a16f2e89da7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815826326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.1815826326
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.4093708567
Short name T2
Test name
Test status
Simulation time 610629997 ps
CPU time 3.87 seconds
Started Jan 24 09:15:43 PM PST 24
Finished Jan 24 09:15:48 PM PST 24
Peak memory 239552 kb
Host smart-a63aa28b-c91c-435a-bc17-4e15fac14cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093708567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.4093708567
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.1982963251
Short name T667
Test name
Test status
Simulation time 2041237696 ps
CPU time 4.31 seconds
Started Jan 24 09:15:36 PM PST 24
Finished Jan 24 09:15:41 PM PST 24
Peak memory 242680 kb
Host smart-b4e60bce-a5d9-42cd-8986-35927a5ac29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982963251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.1982963251
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.3895742179
Short name T81
Test name
Test status
Simulation time 469038337 ps
CPU time 3.94 seconds
Started Jan 24 09:15:39 PM PST 24
Finished Jan 24 09:15:46 PM PST 24
Peak memory 239484 kb
Host smart-1cc0058c-131e-4ec7-95eb-b8547512bdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895742179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.3895742179
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.4035814340
Short name T337
Test name
Test status
Simulation time 148038281 ps
CPU time 4.59 seconds
Started Jan 24 09:15:40 PM PST 24
Finished Jan 24 09:15:46 PM PST 24
Peak memory 243348 kb
Host smart-91a7761f-79ba-4287-baed-7836dbbbaf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035814340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.4035814340
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.3613572031
Short name T494
Test name
Test status
Simulation time 203313521 ps
CPU time 3.94 seconds
Started Jan 24 09:15:38 PM PST 24
Finished Jan 24 09:15:43 PM PST 24
Peak memory 242988 kb
Host smart-bd088924-2b1d-4545-bf3a-a560a7fdec82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613572031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.3613572031
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.142600418
Short name T508
Test name
Test status
Simulation time 497369095 ps
CPU time 4.53 seconds
Started Jan 24 09:15:41 PM PST 24
Finished Jan 24 09:15:48 PM PST 24
Peak memory 244704 kb
Host smart-e6942e57-f9e0-4854-8369-90a77061575a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142600418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.142600418
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.3077348454
Short name T526
Test name
Test status
Simulation time 956930272 ps
CPU time 3.24 seconds
Started Jan 24 08:59:46 PM PST 24
Finished Jan 24 08:59:50 PM PST 24
Peak memory 239828 kb
Host smart-82a9f4e9-68b5-4d36-b5d5-0754933c6047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077348454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.3077348454
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.371323358
Short name T573
Test name
Test status
Simulation time 311975732 ps
CPU time 4.23 seconds
Started Jan 24 08:59:32 PM PST 24
Finished Jan 24 08:59:37 PM PST 24
Peak memory 242500 kb
Host smart-b4a87f5c-94a7-4377-805b-b74dbc6ecd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371323358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.371323358
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.1098375831
Short name T593
Test name
Test status
Simulation time 108706466 ps
CPU time 3.18 seconds
Started Jan 24 08:59:33 PM PST 24
Finished Jan 24 08:59:38 PM PST 24
Peak memory 244208 kb
Host smart-099b935e-96ca-47ed-a863-737b8c55ae9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098375831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.1098375831
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.1214240023
Short name T210
Test name
Test status
Simulation time 299987600 ps
CPU time 6.02 seconds
Started Jan 24 08:59:51 PM PST 24
Finished Jan 24 08:59:58 PM PST 24
Peak memory 239636 kb
Host smart-61365bac-c333-4d52-af22-a6002eebc009
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214240023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.1214240023
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.1178666988
Short name T446
Test name
Test status
Simulation time 325676495 ps
CPU time 5.42 seconds
Started Jan 24 08:59:33 PM PST 24
Finished Jan 24 08:59:40 PM PST 24
Peak memory 243268 kb
Host smart-5c26b74c-c9fb-4319-a708-ee935fd2edf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178666988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.1178666988
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.2081589170
Short name T345
Test name
Test status
Simulation time 493131893 ps
CPU time 5.04 seconds
Started Jan 24 09:28:38 PM PST 24
Finished Jan 24 09:28:44 PM PST 24
Peak memory 244284 kb
Host smart-c551146b-e69e-440d-b4f2-ffcded8ab909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081589170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.2081589170
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.1307254140
Short name T492
Test name
Test status
Simulation time 369438406 ps
CPU time 4 seconds
Started Jan 24 11:31:05 PM PST 24
Finished Jan 24 11:31:10 PM PST 24
Peak memory 243488 kb
Host smart-b61b2dbe-8341-494b-aeb0-0630cbc994be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307254140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.1307254140
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.3621983141
Short name T461
Test name
Test status
Simulation time 449536934 ps
CPU time 3.55 seconds
Started Jan 24 10:39:40 PM PST 24
Finished Jan 24 10:39:45 PM PST 24
Peak memory 243704 kb
Host smart-1d17246c-779b-47c3-bfdd-2c2427983a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621983141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.3621983141
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.2535256271
Short name T261
Test name
Test status
Simulation time 2001627342 ps
CPU time 4.14 seconds
Started Jan 24 09:15:40 PM PST 24
Finished Jan 24 09:15:47 PM PST 24
Peak memory 243388 kb
Host smart-e290d92b-a933-4cda-9cc0-90ace5de3aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535256271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.2535256271
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.277040603
Short name T488
Test name
Test status
Simulation time 1924954923 ps
CPU time 3.81 seconds
Started Jan 24 09:15:40 PM PST 24
Finished Jan 24 09:15:46 PM PST 24
Peak memory 242560 kb
Host smart-a67c7aed-e767-4fdc-ae93-6fe610df4218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277040603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.277040603
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.2364969581
Short name T38
Test name
Test status
Simulation time 478418426 ps
CPU time 4.48 seconds
Started Jan 24 09:15:41 PM PST 24
Finished Jan 24 09:15:48 PM PST 24
Peak memory 239500 kb
Host smart-87ee13b2-bada-4b8e-a3c8-c6b8374d646a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364969581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.2364969581
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.1505067411
Short name T645
Test name
Test status
Simulation time 159451950 ps
CPU time 4 seconds
Started Jan 24 10:02:59 PM PST 24
Finished Jan 24 10:03:04 PM PST 24
Peak memory 244356 kb
Host smart-d65fe8f5-af4a-4c01-939d-85b10c48e4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505067411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.1505067411
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.1726439505
Short name T621
Test name
Test status
Simulation time 78263740 ps
CPU time 1.73 seconds
Started Jan 24 09:00:05 PM PST 24
Finished Jan 24 09:00:08 PM PST 24
Peak memory 239084 kb
Host smart-d2a726ab-0ef5-4c5c-8105-fc98734a5844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726439505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.1726439505
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.1051073512
Short name T223
Test name
Test status
Simulation time 278080216 ps
CPU time 7.84 seconds
Started Jan 24 08:59:56 PM PST 24
Finished Jan 24 09:00:05 PM PST 24
Peak memory 239708 kb
Host smart-de363375-fc83-4b45-a251-d82dc91a4f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051073512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.1051073512
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.569942396
Short name T352
Test name
Test status
Simulation time 2789224473 ps
CPU time 4.83 seconds
Started Jan 25 03:56:49 AM PST 24
Finished Jan 25 03:56:56 AM PST 24
Peak memory 243796 kb
Host smart-7e577b81-d3e0-416b-bf26-660bfca17f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569942396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.569942396
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.1907168612
Short name T523
Test name
Test status
Simulation time 1521280801 ps
CPU time 4 seconds
Started Jan 24 09:55:00 PM PST 24
Finished Jan 24 09:55:07 PM PST 24
Peak memory 239492 kb
Host smart-a6c62dc9-0d58-4216-b9b0-96112dfbcc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907168612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.1907168612
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.970842002
Short name T344
Test name
Test status
Simulation time 2782864776 ps
CPU time 7.08 seconds
Started Jan 24 10:01:26 PM PST 24
Finished Jan 24 10:01:35 PM PST 24
Peak memory 239628 kb
Host smart-afd8f6ac-e83b-42ac-8d7d-6674292ba9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970842002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.970842002
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.3403335375
Short name T598
Test name
Test status
Simulation time 397002823 ps
CPU time 3.22 seconds
Started Jan 25 12:03:51 AM PST 24
Finished Jan 25 12:03:55 AM PST 24
Peak memory 243556 kb
Host smart-bdd70526-9ae5-46c6-b00e-843284d658f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403335375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.3403335375
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.2497755342
Short name T98
Test name
Test status
Simulation time 225461190 ps
CPU time 4.04 seconds
Started Jan 24 09:37:50 PM PST 24
Finished Jan 24 09:37:55 PM PST 24
Peak memory 244408 kb
Host smart-bb20f0bc-7cc6-4933-b516-71eab537c6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497755342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.2497755342
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.2305152240
Short name T703
Test name
Test status
Simulation time 209988738 ps
CPU time 5.08 seconds
Started Jan 24 09:16:03 PM PST 24
Finished Jan 24 09:16:10 PM PST 24
Peak memory 239456 kb
Host smart-99f919ef-d064-4022-80d9-ebcd6cf3f434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305152240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.2305152240
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.772680830
Short name T679
Test name
Test status
Simulation time 1354195534 ps
CPU time 3.8 seconds
Started Jan 24 09:18:51 PM PST 24
Finished Jan 24 09:18:57 PM PST 24
Peak memory 242548 kb
Host smart-a696d654-f2a3-4118-8d3d-08661dea1ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772680830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.772680830
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.1085001366
Short name T680
Test name
Test status
Simulation time 142658927 ps
CPU time 4.25 seconds
Started Jan 25 12:13:06 AM PST 24
Finished Jan 25 12:13:12 AM PST 24
Peak memory 244716 kb
Host smart-ff29c63d-6e47-4ca0-bd1e-c3ca0a425c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085001366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.1085001366
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.716966860
Short name T683
Test name
Test status
Simulation time 1787047926 ps
CPU time 3.76 seconds
Started Jan 24 09:16:02 PM PST 24
Finished Jan 24 09:16:06 PM PST 24
Peak memory 244160 kb
Host smart-0cc5b85e-6e11-4c30-855b-54d8f97fcaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716966860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.716966860
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.4226508514
Short name T228
Test name
Test status
Simulation time 163197823 ps
CPU time 3.46 seconds
Started Jan 24 11:33:05 PM PST 24
Finished Jan 24 11:33:16 PM PST 24
Peak memory 244148 kb
Host smart-307ed051-75cf-468b-a8ae-638e88917350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226508514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.4226508514
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.1574348295
Short name T601
Test name
Test status
Simulation time 183814187 ps
CPU time 1.91 seconds
Started Jan 24 09:00:07 PM PST 24
Finished Jan 24 09:00:10 PM PST 24
Peak memory 239728 kb
Host smart-3b75f707-24c2-430d-8de8-605894de4bc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574348295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.1574348295
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.2284357299
Short name T354
Test name
Test status
Simulation time 237026721 ps
CPU time 4.68 seconds
Started Jan 24 09:00:05 PM PST 24
Finished Jan 24 09:00:11 PM PST 24
Peak memory 242428 kb
Host smart-f9418786-b071-40b7-b36a-d6ad7d86111c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284357299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.2284357299
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.4261757094
Short name T578
Test name
Test status
Simulation time 433014341 ps
CPU time 4.87 seconds
Started Jan 24 09:00:00 PM PST 24
Finished Jan 24 09:00:06 PM PST 24
Peak memory 239600 kb
Host smart-1387f992-fa5d-4de5-827c-8179e68aec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261757094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.4261757094
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.2180728
Short name T521
Test name
Test status
Simulation time 240558783 ps
CPU time 3.47 seconds
Started Jan 24 09:22:20 PM PST 24
Finished Jan 24 09:22:25 PM PST 24
Peak memory 239552 kb
Host smart-63aed41b-1372-46ff-8acb-b4a1b26f111c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.2180728
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.4052377906
Short name T162
Test name
Test status
Simulation time 251334183 ps
CPU time 3.53 seconds
Started Jan 24 09:30:18 PM PST 24
Finished Jan 24 09:30:23 PM PST 24
Peak memory 239556 kb
Host smart-de7767fc-e90c-4f95-a74e-b1dd5d456b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052377906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.4052377906
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.2066759119
Short name T180
Test name
Test status
Simulation time 126440900 ps
CPU time 4.1 seconds
Started Jan 24 11:52:35 PM PST 24
Finished Jan 24 11:52:41 PM PST 24
Peak memory 239504 kb
Host smart-92732e1a-fa7a-4f1d-8b70-909f27e7db57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066759119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.2066759119
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.2189496924
Short name T472
Test name
Test status
Simulation time 513946217 ps
CPU time 3.79 seconds
Started Jan 24 09:16:05 PM PST 24
Finished Jan 24 09:16:17 PM PST 24
Peak memory 244164 kb
Host smart-cd093e5f-20cc-492c-9c23-acbb65e31d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189496924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.2189496924
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.1093767194
Short name T183
Test name
Test status
Simulation time 409302571 ps
CPU time 3.5 seconds
Started Jan 24 09:16:03 PM PST 24
Finished Jan 24 09:16:09 PM PST 24
Peak memory 244024 kb
Host smart-b468be90-3049-419f-8cc4-52e1c1ffb0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093767194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.1093767194
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.179685401
Short name T459
Test name
Test status
Simulation time 152514498 ps
CPU time 3.58 seconds
Started Jan 24 11:23:38 PM PST 24
Finished Jan 24 11:23:43 PM PST 24
Peak memory 244748 kb
Host smart-1afdb471-daab-4462-8061-063c0f30c4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179685401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.179685401
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.1342533859
Short name T624
Test name
Test status
Simulation time 160435279 ps
CPU time 3.44 seconds
Started Jan 24 10:26:56 PM PST 24
Finished Jan 24 10:27:01 PM PST 24
Peak memory 243800 kb
Host smart-6bc244c3-956f-40eb-b118-98d13aac54d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342533859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.1342533859
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.3120625520
Short name T335
Test name
Test status
Simulation time 196557970 ps
CPU time 3.57 seconds
Started Jan 24 09:34:48 PM PST 24
Finished Jan 24 09:34:53 PM PST 24
Peak memory 243524 kb
Host smart-cadadd65-c821-4397-bb1d-5cd67b813e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120625520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.3120625520
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.2810468956
Short name T496
Test name
Test status
Simulation time 2306049767 ps
CPU time 5.04 seconds
Started Jan 24 09:16:06 PM PST 24
Finished Jan 24 09:16:20 PM PST 24
Peak memory 245056 kb
Host smart-1c04a698-2066-440c-afd3-80635027fbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810468956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.2810468956
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.1798805464
Short name T721
Test name
Test status
Simulation time 108627841 ps
CPU time 1.59 seconds
Started Jan 24 09:00:26 PM PST 24
Finished Jan 24 09:00:30 PM PST 24
Peak memory 239700 kb
Host smart-1daf6d84-ece4-42ac-984e-9b2b594c8233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798805464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.1798805464
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.3380250912
Short name T438
Test name
Test status
Simulation time 117843350 ps
CPU time 4.03 seconds
Started Jan 24 09:06:58 PM PST 24
Finished Jan 24 09:07:07 PM PST 24
Peak memory 244500 kb
Host smart-eae2e4d2-1dca-4985-bfe1-ee7c389ce5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380250912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.3380250912
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.1701147002
Short name T467
Test name
Test status
Simulation time 2704329429 ps
CPU time 5.9 seconds
Started Jan 24 09:00:07 PM PST 24
Finished Jan 24 09:00:14 PM PST 24
Peak memory 239728 kb
Host smart-12aca4bd-8799-4bfd-8399-6dd2be67b27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701147002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.1701147002
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.1105086411
Short name T476
Test name
Test status
Simulation time 229625510 ps
CPU time 4.16 seconds
Started Jan 24 09:47:35 PM PST 24
Finished Jan 24 09:47:39 PM PST 24
Peak memory 243748 kb
Host smart-b24c0cf2-6a43-40cf-9d5b-4b19eb8adb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105086411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.1105086411
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.579549920
Short name T671
Test name
Test status
Simulation time 1662356146 ps
CPU time 4.75 seconds
Started Jan 24 09:16:05 PM PST 24
Finished Jan 24 09:16:19 PM PST 24
Peak memory 243240 kb
Host smart-c39d9bfe-25cf-4ffc-952c-fa39935025d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579549920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.579549920
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.2000824010
Short name T338
Test name
Test status
Simulation time 2105165742 ps
CPU time 5.59 seconds
Started Jan 24 09:16:04 PM PST 24
Finished Jan 24 09:16:11 PM PST 24
Peak memory 239520 kb
Host smart-4333da6b-7f37-4161-a1d3-dc4b9d63677c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000824010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.2000824010
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.986109522
Short name T660
Test name
Test status
Simulation time 157121975 ps
CPU time 3.64 seconds
Started Jan 24 09:45:28 PM PST 24
Finished Jan 24 09:45:33 PM PST 24
Peak memory 239536 kb
Host smart-b6b01dc1-f984-4b23-99a3-dbc26c416d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986109522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.986109522
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.3234704931
Short name T585
Test name
Test status
Simulation time 268917624 ps
CPU time 3.99 seconds
Started Jan 24 09:18:52 PM PST 24
Finished Jan 24 09:18:59 PM PST 24
Peak memory 243132 kb
Host smart-01e37451-3328-4474-b1c9-0dc6e42f0be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234704931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.3234704931
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.401699501
Short name T249
Test name
Test status
Simulation time 498303366 ps
CPU time 4.21 seconds
Started Jan 24 11:03:46 PM PST 24
Finished Jan 24 11:03:51 PM PST 24
Peak memory 242920 kb
Host smart-cd0e1a3c-5c34-403d-8bd3-b32a2c495ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401699501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.401699501
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.3534439501
Short name T41
Test name
Test status
Simulation time 133535985 ps
CPU time 5.83 seconds
Started Jan 24 09:54:59 PM PST 24
Finished Jan 24 09:55:07 PM PST 24
Peak memory 243720 kb
Host smart-dfb7653c-5a2a-4223-a266-0e6ec03488b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534439501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.3534439501
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.1807831868
Short name T28
Test name
Test status
Simulation time 171790725 ps
CPU time 4.67 seconds
Started Jan 24 09:16:05 PM PST 24
Finished Jan 24 09:16:18 PM PST 24
Peak memory 242584 kb
Host smart-afad9e32-69c8-4884-b4ac-0b13f5c957fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807831868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.1807831868
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.1751304338
Short name T202
Test name
Test status
Simulation time 162549428 ps
CPU time 1.79 seconds
Started Jan 24 09:00:28 PM PST 24
Finished Jan 24 09:00:31 PM PST 24
Peak memory 239104 kb
Host smart-de2fe073-7bac-4b00-b9c5-081139617406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751304338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.1751304338
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.448514998
Short name T722
Test name
Test status
Simulation time 474913056 ps
CPU time 3.59 seconds
Started Jan 24 09:00:26 PM PST 24
Finished Jan 24 09:00:32 PM PST 24
Peak memory 242628 kb
Host smart-99224d9d-176e-425f-a7d6-42dee8c3b824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448514998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.448514998
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.2849482084
Short name T65
Test name
Test status
Simulation time 1998834370 ps
CPU time 3.81 seconds
Started Jan 24 09:00:26 PM PST 24
Finished Jan 24 09:00:32 PM PST 24
Peak memory 244492 kb
Host smart-f83a0977-54f0-4055-bc68-514e6b760a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849482084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.2849482084
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.1126899178
Short name T224
Test name
Test status
Simulation time 1101029974 ps
CPU time 10.73 seconds
Started Jan 24 09:00:25 PM PST 24
Finished Jan 24 09:00:39 PM PST 24
Peak memory 239636 kb
Host smart-f1e5f726-e229-45eb-ab19-0780235f1815
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1126899178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.1126899178
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.49813253
Short name T42
Test name
Test status
Simulation time 153541121 ps
CPU time 4.45 seconds
Started Jan 24 09:16:05 PM PST 24
Finished Jan 24 09:16:18 PM PST 24
Peak memory 239516 kb
Host smart-fd0b7b58-5546-41b8-b06c-e955123166a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49813253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.49813253
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.2971148524
Short name T696
Test name
Test status
Simulation time 254488410 ps
CPU time 4.55 seconds
Started Jan 24 09:16:17 PM PST 24
Finished Jan 24 09:16:28 PM PST 24
Peak memory 242312 kb
Host smart-7f9ff6be-f88e-4f93-bc26-49ba333af934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971148524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.2971148524
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.3438025243
Short name T451
Test name
Test status
Simulation time 2950565248 ps
CPU time 5.9 seconds
Started Jan 24 09:16:24 PM PST 24
Finished Jan 24 09:16:32 PM PST 24
Peak memory 244120 kb
Host smart-872c06db-42a7-45fa-92bd-fc0f8c4ce034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438025243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.3438025243
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.1430354950
Short name T480
Test name
Test status
Simulation time 302096137 ps
CPU time 4.93 seconds
Started Jan 24 09:16:18 PM PST 24
Finished Jan 24 09:16:29 PM PST 24
Peak memory 243268 kb
Host smart-6ebd789a-ff2a-498d-b955-df2098ec31c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430354950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.1430354950
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.3983902018
Short name T702
Test name
Test status
Simulation time 184411840 ps
CPU time 3.86 seconds
Started Jan 24 09:16:20 PM PST 24
Finished Jan 24 09:16:30 PM PST 24
Peak memory 239456 kb
Host smart-890c0789-9836-4544-8943-861373050faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983902018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.3983902018
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.1255055466
Short name T628
Test name
Test status
Simulation time 1771797270 ps
CPU time 6.82 seconds
Started Jan 24 09:16:18 PM PST 24
Finished Jan 24 09:16:31 PM PST 24
Peak memory 244780 kb
Host smart-10dd36d3-63d0-4141-9522-dbcff745b09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255055466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.1255055466
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.2105251369
Short name T582
Test name
Test status
Simulation time 288368964 ps
CPU time 3.64 seconds
Started Jan 24 09:16:21 PM PST 24
Finished Jan 24 09:16:29 PM PST 24
Peak memory 243036 kb
Host smart-077cc5ab-bd4b-4524-abfc-64dee367ee9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105251369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.2105251369
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.1342135909
Short name T44
Test name
Test status
Simulation time 144976174 ps
CPU time 3.87 seconds
Started Jan 24 09:16:24 PM PST 24
Finished Jan 24 09:16:30 PM PST 24
Peak memory 246652 kb
Host smart-4c25af0e-706d-492b-8ac4-31c28a161469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342135909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.1342135909
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.1123897506
Short name T343
Test name
Test status
Simulation time 455096443 ps
CPU time 4.6 seconds
Started Jan 24 09:16:24 PM PST 24
Finished Jan 24 09:16:31 PM PST 24
Peak memory 243500 kb
Host smart-554d3bc6-e593-4481-8796-292376567d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123897506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.1123897506
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.2472155242
Short name T483
Test name
Test status
Simulation time 593147359 ps
CPU time 4.31 seconds
Started Jan 24 09:16:36 PM PST 24
Finished Jan 24 09:16:41 PM PST 24
Peak memory 242936 kb
Host smart-0429f53a-2c14-42ba-92de-9b11c41a4a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472155242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.2472155242
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.506768614
Short name T443
Test name
Test status
Simulation time 75776049 ps
CPU time 2 seconds
Started Jan 24 09:00:47 PM PST 24
Finished Jan 24 09:00:49 PM PST 24
Peak memory 239780 kb
Host smart-28deb331-2c7a-4290-b602-c27d468920c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506768614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.506768614
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.2337038143
Short name T532
Test name
Test status
Simulation time 211371069 ps
CPU time 3.48 seconds
Started Jan 24 09:00:25 PM PST 24
Finished Jan 24 09:00:31 PM PST 24
Peak memory 244008 kb
Host smart-7e64b192-8a2f-4d38-9e5f-f76948c363e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337038143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.2337038143
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.4244634708
Short name T704
Test name
Test status
Simulation time 2109707771 ps
CPU time 5.39 seconds
Started Jan 24 09:00:38 PM PST 24
Finished Jan 24 09:00:45 PM PST 24
Peak memory 239652 kb
Host smart-4dcb243b-b7a7-415a-a94d-caf15239df08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4244634708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.4244634708
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.3347963930
Short name T613
Test name
Test status
Simulation time 2299720170 ps
CPU time 4.09 seconds
Started Jan 24 09:00:26 PM PST 24
Finished Jan 24 09:00:32 PM PST 24
Peak memory 243448 kb
Host smart-da61e80a-f082-4eef-a41f-2a76a3d7619c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347963930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.3347963930
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.3943368285
Short name T524
Test name
Test status
Simulation time 2758313928 ps
CPU time 5.77 seconds
Started Jan 24 09:16:40 PM PST 24
Finished Jan 24 09:16:47 PM PST 24
Peak memory 244028 kb
Host smart-39ce42e1-2da9-4202-9bef-cd44312e8645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943368285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.3943368285
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.1572184449
Short name T688
Test name
Test status
Simulation time 144405794 ps
CPU time 3.65 seconds
Started Jan 24 09:16:37 PM PST 24
Finished Jan 24 09:16:41 PM PST 24
Peak memory 243380 kb
Host smart-a042ec0f-d444-448c-abcb-12b4c5f42391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572184449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.1572184449
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.1012421580
Short name T719
Test name
Test status
Simulation time 1870695005 ps
CPU time 4.47 seconds
Started Jan 24 09:16:35 PM PST 24
Finished Jan 24 09:16:41 PM PST 24
Peak memory 244060 kb
Host smart-e078b63e-03fc-4914-8c0e-0c378f9889ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012421580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.1012421580
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.540965637
Short name T544
Test name
Test status
Simulation time 163965977 ps
CPU time 4.07 seconds
Started Jan 24 09:16:40 PM PST 24
Finished Jan 24 09:16:45 PM PST 24
Peak memory 243704 kb
Host smart-e7b3b286-466b-443d-9c98-0572188301fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540965637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.540965637
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.307348610
Short name T161
Test name
Test status
Simulation time 220293093 ps
CPU time 3.44 seconds
Started Jan 24 09:16:36 PM PST 24
Finished Jan 24 09:16:41 PM PST 24
Peak memory 239560 kb
Host smart-4a9c129b-12d3-48fa-bb32-aaa9fe5b2dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307348610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.307348610
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.2359017716
Short name T454
Test name
Test status
Simulation time 110060885 ps
CPU time 3.92 seconds
Started Jan 24 09:16:39 PM PST 24
Finished Jan 24 09:16:44 PM PST 24
Peak memory 243472 kb
Host smart-72464083-da72-4f43-8717-feef11cf5af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359017716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.2359017716
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.1106629931
Short name T177
Test name
Test status
Simulation time 261910313 ps
CPU time 4.73 seconds
Started Jan 24 09:16:38 PM PST 24
Finished Jan 24 09:16:44 PM PST 24
Peak memory 239508 kb
Host smart-e472ae5b-187a-4891-8c8e-62062fceef12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106629931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.1106629931
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.3486805797
Short name T635
Test name
Test status
Simulation time 235120690 ps
CPU time 4.24 seconds
Started Jan 24 09:16:36 PM PST 24
Finished Jan 24 09:16:41 PM PST 24
Peak memory 239488 kb
Host smart-9403b786-5c67-40f6-9caf-336dba074feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486805797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.3486805797
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.4143533
Short name T505
Test name
Test status
Simulation time 121833689 ps
CPU time 2.22 seconds
Started Jan 24 08:54:16 PM PST 24
Finished Jan 24 08:54:19 PM PST 24
Peak memory 239732 kb
Host smart-d8e38a0e-b5bd-4770-b832-d1ee75fbe372
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.4143533
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.801700623
Short name T609
Test name
Test status
Simulation time 211416692 ps
CPU time 3.87 seconds
Started Jan 24 08:54:04 PM PST 24
Finished Jan 24 08:54:10 PM PST 24
Peak memory 243884 kb
Host smart-38efa554-a95b-4487-b17e-a6182734220c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801700623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.801700623
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.1801216689
Short name T211
Test name
Test status
Simulation time 207045410 ps
CPU time 5.42 seconds
Started Jan 24 08:54:04 PM PST 24
Finished Jan 24 08:54:10 PM PST 24
Peak memory 239712 kb
Host smart-668d6130-701b-4049-9fad-5b231b091b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801216689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.1801216689
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.3804622436
Short name T518
Test name
Test status
Simulation time 837881964 ps
CPU time 2.18 seconds
Started Jan 24 09:01:05 PM PST 24
Finished Jan 24 09:01:11 PM PST 24
Peak memory 239652 kb
Host smart-e67f8df7-9ba3-44bb-8bd2-8d8868f3978b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804622436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.3804622436
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.2721776044
Short name T466
Test name
Test status
Simulation time 275464420 ps
CPU time 3.71 seconds
Started Jan 24 09:00:53 PM PST 24
Finished Jan 24 09:01:01 PM PST 24
Peak memory 243592 kb
Host smart-6bb2042d-d6f5-40ae-8343-a96b5ee08705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721776044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.2721776044
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.3635999069
Short name T720
Test name
Test status
Simulation time 167589822 ps
CPU time 5.47 seconds
Started Jan 24 09:00:48 PM PST 24
Finished Jan 24 09:00:55 PM PST 24
Peak memory 239680 kb
Host smart-c529c9f8-73c6-40f4-86bb-44404de98d3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3635999069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.3635999069
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.1613975812
Short name T232
Test name
Test status
Simulation time 1154138369 ps
CPU time 11.19 seconds
Started Jan 24 09:00:53 PM PST 24
Finished Jan 24 09:01:08 PM PST 24
Peak memory 246944 kb
Host smart-b75b7fb2-12cf-4fc5-97ee-5b37bda5e474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613975812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.1613975812
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.98521705
Short name T663
Test name
Test status
Simulation time 94280868 ps
CPU time 1.72 seconds
Started Jan 24 09:01:27 PM PST 24
Finished Jan 24 09:01:30 PM PST 24
Peak memory 239716 kb
Host smart-9779f7ba-02d2-42b3-b276-d9df980ee2f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98521705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.98521705
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.1404792568
Short name T662
Test name
Test status
Simulation time 520036243 ps
CPU time 4.47 seconds
Started Jan 24 09:01:06 PM PST 24
Finished Jan 24 09:01:15 PM PST 24
Peak memory 239488 kb
Host smart-2bdd5f29-d377-4d95-966e-e0e408a5b8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404792568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.1404792568
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.466832990
Short name T468
Test name
Test status
Simulation time 232221308 ps
CPU time 4.19 seconds
Started Jan 24 09:01:06 PM PST 24
Finished Jan 24 09:01:14 PM PST 24
Peak memory 239624 kb
Host smart-594d8778-d885-4a95-8f0b-3ee7545e4e5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466832990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.466832990
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.2276994568
Short name T564
Test name
Test status
Simulation time 577873243 ps
CPU time 3.81 seconds
Started Jan 24 09:01:07 PM PST 24
Finished Jan 24 09:01:17 PM PST 24
Peak memory 246108 kb
Host smart-dfc525dc-733e-4b41-899b-ab42bbea00b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276994568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.2276994568
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.4141078031
Short name T493
Test name
Test status
Simulation time 582900888 ps
CPU time 1.69 seconds
Started Jan 24 09:01:35 PM PST 24
Finished Jan 24 09:01:38 PM PST 24
Peak memory 239548 kb
Host smart-617eea4e-5665-450d-98ef-ac560b8bbc94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141078031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.4141078031
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.407953602
Short name T84
Test name
Test status
Simulation time 312344444 ps
CPU time 4.05 seconds
Started Jan 24 09:01:27 PM PST 24
Finished Jan 24 09:01:32 PM PST 24
Peak memory 243336 kb
Host smart-fca6ab2e-3b75-4a80-a5f7-f2ba219a6507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407953602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.407953602
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.2168658211
Short name T226
Test name
Test status
Simulation time 148586568 ps
CPU time 5.18 seconds
Started Jan 24 09:19:09 PM PST 24
Finished Jan 24 09:19:16 PM PST 24
Peak memory 239580 kb
Host smart-42afc299-0562-4431-ad9f-a3f064a28b27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2168658211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.2168658211
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.2359951884
Short name T233
Test name
Test status
Simulation time 6460018046 ps
CPU time 15.39 seconds
Started Jan 24 09:01:23 PM PST 24
Finished Jan 24 09:01:41 PM PST 24
Peak memory 239748 kb
Host smart-ef0f3848-1786-4af4-ac10-d56d1d704e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359951884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.2359951884
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.4090985679
Short name T542
Test name
Test status
Simulation time 70649975 ps
CPU time 1.53 seconds
Started Jan 24 09:01:49 PM PST 24
Finished Jan 24 09:01:54 PM PST 24
Peak memory 239392 kb
Host smart-b57b4c59-beb5-4013-8d7f-385d185c498f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090985679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.4090985679
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.1887256597
Short name T333
Test name
Test status
Simulation time 599547928 ps
CPU time 3.86 seconds
Started Jan 24 09:01:49 PM PST 24
Finished Jan 24 09:01:56 PM PST 24
Peak memory 239524 kb
Host smart-a14e0ce6-e73f-4571-a5fc-45dc276f1c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887256597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.1887256597
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.3392379136
Short name T235
Test name
Test status
Simulation time 152407278 ps
CPU time 4.55 seconds
Started Jan 24 10:09:16 PM PST 24
Finished Jan 24 10:09:21 PM PST 24
Peak memory 239572 kb
Host smart-7cbcc24d-a7a6-4e56-a02f-3fa817431211
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3392379136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.3392379136
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.2334711980
Short name T340
Test name
Test status
Simulation time 528796191 ps
CPU time 3.25 seconds
Started Jan 24 09:01:55 PM PST 24
Finished Jan 24 09:01:59 PM PST 24
Peak memory 239968 kb
Host smart-4f4b4be5-1cd9-4770-bd02-fabbd68fb5e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334711980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.2334711980
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.577373812
Short name T594
Test name
Test status
Simulation time 544359386 ps
CPU time 3.47 seconds
Started Jan 24 09:01:48 PM PST 24
Finished Jan 24 09:01:55 PM PST 24
Peak memory 243568 kb
Host smart-a9e98e19-9e7f-4489-9a62-b347630f0c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577373812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.577373812
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.1129882924
Short name T4
Test name
Test status
Simulation time 259987998 ps
CPU time 9.16 seconds
Started Jan 24 10:16:34 PM PST 24
Finished Jan 24 10:16:45 PM PST 24
Peak memory 246676 kb
Host smart-07a55117-90cb-4274-b69d-775421046c38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129882924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.1129882924
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.229123127
Short name T346
Test name
Test status
Simulation time 150496081 ps
CPU time 4.39 seconds
Started Jan 24 09:01:49 PM PST 24
Finished Jan 24 09:01:56 PM PST 24
Peak memory 239716 kb
Host smart-7fa0722d-278b-4480-a7ff-5172f80ce055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229123127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.229123127
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.2569832896
Short name T611
Test name
Test status
Simulation time 97892340 ps
CPU time 1.76 seconds
Started Jan 24 09:02:07 PM PST 24
Finished Jan 24 09:02:09 PM PST 24
Peak memory 239816 kb
Host smart-8fe20135-a6ee-4a93-8fcb-f98ec0e8073f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569832896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.2569832896
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.548227221
Short name T248
Test name
Test status
Simulation time 1959489370 ps
CPU time 6.04 seconds
Started Jan 24 10:26:59 PM PST 24
Finished Jan 24 10:27:06 PM PST 24
Peak memory 243436 kb
Host smart-351c65cf-224c-4b87-a81d-321c1658eeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548227221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.548227221
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.2612637620
Short name T641
Test name
Test status
Simulation time 3946879506 ps
CPU time 7.81 seconds
Started Jan 24 09:02:10 PM PST 24
Finished Jan 24 09:02:20 PM PST 24
Peak memory 246652 kb
Host smart-ead2de09-67db-4058-9817-1f06ab936cd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2612637620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.2612637620
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.1788889930
Short name T70
Test name
Test status
Simulation time 377969742 ps
CPU time 4.32 seconds
Started Jan 24 09:01:53 PM PST 24
Finished Jan 24 09:02:00 PM PST 24
Peak memory 239720 kb
Host smart-a5b47422-c34c-43ee-acb8-42931b0f4b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788889930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.1788889930
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.1093949194
Short name T528
Test name
Test status
Simulation time 69335800 ps
CPU time 1.98 seconds
Started Jan 24 09:02:46 PM PST 24
Finished Jan 24 09:02:49 PM PST 24
Peak memory 239928 kb
Host smart-86a34def-8f6e-4246-bcfe-83924fbf4bd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093949194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.1093949194
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.646596996
Short name T239
Test name
Test status
Simulation time 755114060 ps
CPU time 7.66 seconds
Started Jan 24 09:02:27 PM PST 24
Finished Jan 24 09:02:35 PM PST 24
Peak memory 239644 kb
Host smart-6bb8292c-903b-4bd6-955f-1246d0625afd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=646596996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.646596996
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.2483407392
Short name T478
Test name
Test status
Simulation time 171942555 ps
CPU time 1.8 seconds
Started Jan 24 09:03:01 PM PST 24
Finished Jan 24 09:03:04 PM PST 24
Peak memory 239300 kb
Host smart-2f5095a8-48ed-4c4e-9798-0c08430ef276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483407392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.2483407392
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.989583941
Short name T649
Test name
Test status
Simulation time 2615012872 ps
CPU time 5.42 seconds
Started Jan 24 09:02:58 PM PST 24
Finished Jan 24 09:03:04 PM PST 24
Peak memory 245224 kb
Host smart-5ce91dd9-9b47-4691-8085-3262c7e35a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989583941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.989583941
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.4193299312
Short name T234
Test name
Test status
Simulation time 130612285 ps
CPU time 3.9 seconds
Started Jan 24 09:02:57 PM PST 24
Finished Jan 24 09:03:02 PM PST 24
Peak memory 239600 kb
Host smart-f598a78a-67c2-4abf-a82d-080dd89593e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4193299312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.4193299312
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.515638896
Short name T503
Test name
Test status
Simulation time 264296251 ps
CPU time 8.47 seconds
Started Jan 24 09:02:56 PM PST 24
Finished Jan 24 09:03:05 PM PST 24
Peak memory 239680 kb
Host smart-cc020052-4885-4cc0-9e87-5f5943eb6ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515638896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.515638896
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.1677755759
Short name T571
Test name
Test status
Simulation time 63355433 ps
CPU time 1.86 seconds
Started Jan 24 09:03:15 PM PST 24
Finished Jan 24 09:03:18 PM PST 24
Peak memory 239812 kb
Host smart-dceb7948-056a-4e84-8514-bbe43fab078e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677755759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.1677755759
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.1621626459
Short name T672
Test name
Test status
Simulation time 470714511 ps
CPU time 5.31 seconds
Started Jan 24 09:02:57 PM PST 24
Finished Jan 24 09:03:03 PM PST 24
Peak memory 243504 kb
Host smart-57c94a84-a3da-4aa7-a482-ca45416a60a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621626459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.1621626459
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.604411595
Short name T231
Test name
Test status
Simulation time 1734488060 ps
CPU time 4.11 seconds
Started Jan 24 09:03:07 PM PST 24
Finished Jan 24 09:03:12 PM PST 24
Peak memory 239652 kb
Host smart-580798ee-e6a2-415a-afe9-3a733ff6a0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604411595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.604411595
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.3220798467
Short name T535
Test name
Test status
Simulation time 101440382 ps
CPU time 1.53 seconds
Started Jan 24 09:03:13 PM PST 24
Finished Jan 24 09:03:15 PM PST 24
Peak memory 239564 kb
Host smart-42be1eca-d69c-4d08-9984-fc6c7694bd4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220798467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.3220798467
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.3723816387
Short name T481
Test name
Test status
Simulation time 191840125 ps
CPU time 3.97 seconds
Started Jan 24 10:00:57 PM PST 24
Finished Jan 24 10:01:05 PM PST 24
Peak memory 243432 kb
Host smart-9b1693d0-24ad-450f-8392-c3a35069e576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723816387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.3723816387
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.4246636544
Short name T630
Test name
Test status
Simulation time 1830834942 ps
CPU time 13.82 seconds
Started Jan 24 09:03:16 PM PST 24
Finished Jan 24 09:03:31 PM PST 24
Peak memory 247608 kb
Host smart-bd922cc3-cfa3-4c63-90f1-d185134ba1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246636544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.4246636544
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.25813414
Short name T63
Test name
Test status
Simulation time 153515073 ps
CPU time 4.65 seconds
Started Jan 24 09:54:14 PM PST 24
Finished Jan 24 09:54:19 PM PST 24
Peak memory 244500 kb
Host smart-b336c035-5a6c-4e3d-8a9f-d09be8073327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25813414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.25813414
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.1905364961
Short name T100
Test name
Test status
Simulation time 520467080 ps
CPU time 4.94 seconds
Started Jan 24 09:34:02 PM PST 24
Finished Jan 24 09:34:09 PM PST 24
Peak memory 239644 kb
Host smart-ee17a2d5-e337-4f9e-a497-d8bdb09527fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905364961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.1905364961
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.4094997889
Short name T458
Test name
Test status
Simulation time 193019022 ps
CPU time 1.89 seconds
Started Jan 24 09:16:33 PM PST 24
Finished Jan 24 09:16:35 PM PST 24
Peak memory 239880 kb
Host smart-6e5e8481-d075-45fd-bc3f-951fbb8d9760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094997889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.4094997889
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.201795919
Short name T705
Test name
Test status
Simulation time 183420566 ps
CPU time 4.08 seconds
Started Jan 24 08:54:16 PM PST 24
Finished Jan 24 08:54:21 PM PST 24
Peak memory 243724 kb
Host smart-14bc85d1-f34f-4424-bd27-faf616768b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201795919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.201795919
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.84356444
Short name T238
Test name
Test status
Simulation time 168930464 ps
CPU time 4.62 seconds
Started Jan 24 08:54:31 PM PST 24
Finished Jan 24 08:54:37 PM PST 24
Peak memory 239600 kb
Host smart-ae20dc13-8bd9-4203-8ae1-42ab0330b512
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=84356444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.84356444
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.3676007973
Short name T243
Test name
Test status
Simulation time 17207051777 ps
CPU time 154.06 seconds
Started Jan 24 09:24:11 PM PST 24
Finished Jan 24 09:26:50 PM PST 24
Peak memory 269520 kb
Host smart-4ce485dc-814d-402e-b855-4b8c26344bd4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676007973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.3676007973
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.1376895996
Short name T208
Test name
Test status
Simulation time 1731614117 ps
CPU time 10.6 seconds
Started Jan 24 09:07:11 PM PST 24
Finished Jan 24 09:07:22 PM PST 24
Peak memory 239672 kb
Host smart-4587cec5-c7fa-473d-a021-1c47c838936c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376895996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.1376895996
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.546537453
Short name T529
Test name
Test status
Simulation time 70240642 ps
CPU time 1.83 seconds
Started Jan 24 09:52:07 PM PST 24
Finished Jan 24 09:52:10 PM PST 24
Peak memory 239344 kb
Host smart-096909ab-07f9-44b3-abc5-f8b930f5d78f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546537453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.546537453
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.3609771658
Short name T88
Test name
Test status
Simulation time 293561513 ps
CPU time 4.45 seconds
Started Jan 24 09:20:04 PM PST 24
Finished Jan 24 09:20:09 PM PST 24
Peak memory 247680 kb
Host smart-e87a4d6f-d7e1-497b-b04d-74ba825efb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609771658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.3609771658
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.3773717851
Short name T104
Test name
Test status
Simulation time 333713360 ps
CPU time 4.65 seconds
Started Jan 24 09:03:14 PM PST 24
Finished Jan 24 09:03:20 PM PST 24
Peak memory 239572 kb
Host smart-ec15184f-6bba-4709-92d9-ebdb788c7265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773717851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.3773717851
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.2119105427
Short name T675
Test name
Test status
Simulation time 136210043 ps
CPU time 1.82 seconds
Started Jan 24 09:03:19 PM PST 24
Finished Jan 24 09:03:23 PM PST 24
Peak memory 239780 kb
Host smart-3d2ff8bf-ebf8-4df0-adf1-27cea3cf503d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119105427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.2119105427
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.224137252
Short name T464
Test name
Test status
Simulation time 1658876350 ps
CPU time 5.49 seconds
Started Jan 24 11:23:13 PM PST 24
Finished Jan 24 11:23:20 PM PST 24
Peak memory 239480 kb
Host smart-cf3e9614-2aa7-4a25-bf67-310ab5a73604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224137252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.224137252
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.2864025576
Short name T546
Test name
Test status
Simulation time 714940157 ps
CPU time 5.29 seconds
Started Jan 24 09:14:36 PM PST 24
Finished Jan 24 09:14:42 PM PST 24
Peak memory 239576 kb
Host smart-ce3559f7-65ae-4f7b-ac28-5f0ba94d991d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864025576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.2864025576
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.424825293
Short name T442
Test name
Test status
Simulation time 2275489370 ps
CPU time 7.95 seconds
Started Jan 24 09:24:05 PM PST 24
Finished Jan 24 09:24:14 PM PST 24
Peak memory 239816 kb
Host smart-54d52b8c-4772-4c3d-b572-79f98c16404f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=424825293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.424825293
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.2470736495
Short name T629
Test name
Test status
Simulation time 384123191 ps
CPU time 2.68 seconds
Started Jan 24 09:03:21 PM PST 24
Finished Jan 24 09:03:25 PM PST 24
Peak memory 242848 kb
Host smart-d5ea80af-eb14-429b-8202-9fba0e5452e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470736495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.2470736495
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.996346026
Short name T245
Test name
Test status
Simulation time 128216626 ps
CPU time 1.96 seconds
Started Jan 24 09:03:58 PM PST 24
Finished Jan 24 09:04:14 PM PST 24
Peak memory 239992 kb
Host smart-9154b4f7-c6ec-47c7-9e7f-90dc090636bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996346026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.996346026
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.2626231194
Short name T36
Test name
Test status
Simulation time 263918599 ps
CPU time 3.68 seconds
Started Jan 24 09:15:43 PM PST 24
Finished Jan 24 09:15:48 PM PST 24
Peak memory 243344 kb
Host smart-0bb14f53-8645-4b6f-a829-971daebfd57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626231194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.2626231194
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.1354311599
Short name T539
Test name
Test status
Simulation time 74990641 ps
CPU time 2.47 seconds
Started Jan 24 09:03:58 PM PST 24
Finished Jan 24 09:04:14 PM PST 24
Peak memory 239504 kb
Host smart-3c398d21-1c79-43e5-95ae-a977498d25c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1354311599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.1354311599
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.4022841693
Short name T550
Test name
Test status
Simulation time 330474218 ps
CPU time 4.51 seconds
Started Jan 24 09:03:35 PM PST 24
Finished Jan 24 09:03:40 PM PST 24
Peak memory 239620 kb
Host smart-5d083364-289f-4e47-8163-6e5281aa26aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022841693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.4022841693
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.2777229467
Short name T280
Test name
Test status
Simulation time 172485194 ps
CPU time 1.61 seconds
Started Jan 24 09:04:12 PM PST 24
Finished Jan 24 09:04:23 PM PST 24
Peak memory 239612 kb
Host smart-a2e74422-1d58-4e18-a8d3-6cd552f91ef7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777229467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.2777229467
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.3463714138
Short name T514
Test name
Test status
Simulation time 347129441 ps
CPU time 4.21 seconds
Started Jan 24 09:03:55 PM PST 24
Finished Jan 24 09:04:02 PM PST 24
Peak memory 244752 kb
Host smart-2085d088-6135-4cab-98b8-d17ba1016d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463714138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.3463714138
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.3938453572
Short name T67
Test name
Test status
Simulation time 1156223016 ps
CPU time 3.35 seconds
Started Jan 24 09:54:35 PM PST 24
Finished Jan 24 09:54:48 PM PST 24
Peak memory 242876 kb
Host smart-b191019e-66f9-4649-9ddd-bbd94d61d87c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3938453572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.3938453572
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.3653352771
Short name T605
Test name
Test status
Simulation time 130011945 ps
CPU time 5.24 seconds
Started Jan 24 09:03:58 PM PST 24
Finished Jan 24 09:04:11 PM PST 24
Peak memory 239612 kb
Host smart-cea46302-c4a7-401a-bfc7-13948537ad36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653352771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.3653352771
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.4080829826
Short name T99
Test name
Test status
Simulation time 566040204 ps
CPU time 1.76 seconds
Started Jan 24 09:04:40 PM PST 24
Finished Jan 24 09:04:43 PM PST 24
Peak memory 239092 kb
Host smart-ad81c614-1494-40a1-b84b-bc01296a0ab8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080829826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.4080829826
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.1361150699
Short name T717
Test name
Test status
Simulation time 657458225 ps
CPU time 3.92 seconds
Started Jan 24 09:12:47 PM PST 24
Finished Jan 24 09:12:52 PM PST 24
Peak memory 239580 kb
Host smart-625c85a6-86cf-4c47-8d72-b0ca5041c2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361150699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.1361150699
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.849544544
Short name T687
Test name
Test status
Simulation time 331466703 ps
CPU time 5.84 seconds
Started Jan 24 09:04:15 PM PST 24
Finished Jan 24 09:04:29 PM PST 24
Peak memory 239636 kb
Host smart-88b4bd44-e828-4309-b637-e3bec989c449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849544544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.849544544
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.3324423567
Short name T600
Test name
Test status
Simulation time 60080697 ps
CPU time 1.74 seconds
Started Jan 24 09:04:30 PM PST 24
Finished Jan 24 09:04:33 PM PST 24
Peak memory 239664 kb
Host smart-f45c57b2-ed50-4b57-b09c-439991a0770b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324423567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.3324423567
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.114712549
Short name T176
Test name
Test status
Simulation time 344912356 ps
CPU time 3.96 seconds
Started Jan 24 09:33:57 PM PST 24
Finished Jan 24 09:34:03 PM PST 24
Peak memory 244628 kb
Host smart-e8768cd0-9eba-42b1-ae42-c070d2285b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114712549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.114712549
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.2467660698
Short name T633
Test name
Test status
Simulation time 442997297 ps
CPU time 4.47 seconds
Started Jan 24 09:04:40 PM PST 24
Finished Jan 24 09:04:46 PM PST 24
Peak memory 239580 kb
Host smart-24f64c1f-c13d-4785-bf70-3e666a7c32ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467660698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.2467660698
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.228407803
Short name T237
Test name
Test status
Simulation time 472820280 ps
CPU time 10.38 seconds
Started Jan 24 09:04:32 PM PST 24
Finished Jan 24 09:04:43 PM PST 24
Peak memory 239624 kb
Host smart-29b6c3a7-6d06-4f3b-879f-d0721b8960c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228407803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.228407803
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.1565339405
Short name T608
Test name
Test status
Simulation time 99871060 ps
CPU time 1.71 seconds
Started Jan 24 09:06:50 PM PST 24
Finished Jan 24 09:06:53 PM PST 24
Peak memory 239732 kb
Host smart-d9a541bf-1e2a-4330-8fcc-24975c49f09b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565339405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.1565339405
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.1310658601
Short name T188
Test name
Test status
Simulation time 135252285 ps
CPU time 3.16 seconds
Started Jan 24 09:04:32 PM PST 24
Finished Jan 24 09:04:37 PM PST 24
Peak memory 243880 kb
Host smart-df42a61d-840f-4620-9168-d7d80ec35048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310658601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.1310658601
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.767307964
Short name T502
Test name
Test status
Simulation time 520809817 ps
CPU time 5.3 seconds
Started Jan 24 09:06:49 PM PST 24
Finished Jan 24 09:06:55 PM PST 24
Peak memory 239668 kb
Host smart-c3f732a9-357a-4ded-b17d-56a20a363f8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=767307964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.767307964
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.1541082066
Short name T595
Test name
Test status
Simulation time 363113655 ps
CPU time 4.66 seconds
Started Jan 24 10:05:17 PM PST 24
Finished Jan 24 10:05:23 PM PST 24
Peak memory 239500 kb
Host smart-54b25326-4871-430d-89d2-9a892123ad6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541082066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.1541082066
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.1335166972
Short name T178
Test name
Test status
Simulation time 759811132 ps
CPU time 2.65 seconds
Started Jan 24 09:07:07 PM PST 24
Finished Jan 24 09:07:10 PM PST 24
Peak memory 239860 kb
Host smart-bfdfb40e-a482-478a-ab43-cfb685786644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335166972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.1335166972
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.2646992421
Short name T332
Test name
Test status
Simulation time 664595558 ps
CPU time 10.57 seconds
Started Jan 24 09:06:58 PM PST 24
Finished Jan 24 09:07:14 PM PST 24
Peak memory 239480 kb
Host smart-859a2296-2dc0-4819-937a-c99de804a5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646992421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.2646992421
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.38973620
Short name T587
Test name
Test status
Simulation time 291593488 ps
CPU time 9.15 seconds
Started Jan 24 09:06:48 PM PST 24
Finished Jan 24 09:06:58 PM PST 24
Peak memory 239616 kb
Host smart-bc6d927b-1dd5-482b-bf4a-312ff2b29bb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38973620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.38973620
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.4152717365
Short name T557
Test name
Test status
Simulation time 3146034689 ps
CPU time 4.73 seconds
Started Jan 24 09:06:48 PM PST 24
Finished Jan 24 09:06:53 PM PST 24
Peak memory 239692 kb
Host smart-b8aec494-932d-4549-ac26-f8a926b01256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152717365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.4152717365
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.2713878226
Short name T626
Test name
Test status
Simulation time 871092330 ps
CPU time 2.14 seconds
Started Jan 24 09:07:14 PM PST 24
Finished Jan 24 09:07:17 PM PST 24
Peak memory 239892 kb
Host smart-5d243c04-62eb-4906-a6dc-76f2aec61e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713878226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.2713878226
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.2108710344
Short name T580
Test name
Test status
Simulation time 166800633 ps
CPU time 4.84 seconds
Started Jan 24 09:07:12 PM PST 24
Finished Jan 24 09:07:18 PM PST 24
Peak memory 244476 kb
Host smart-5c00fbf6-bf10-4d41-9c0c-3a6678f1e3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108710344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.2108710344
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.2060924609
Short name T657
Test name
Test status
Simulation time 874281684 ps
CPU time 6.33 seconds
Started Jan 24 09:07:07 PM PST 24
Finished Jan 24 09:07:14 PM PST 24
Peak memory 239640 kb
Host smart-39f52ab1-fa58-43c9-9e6e-3c3038fb208c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060924609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.2060924609
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.1611586511
Short name T569
Test name
Test status
Simulation time 121390723 ps
CPU time 2.07 seconds
Started Jan 24 10:51:27 PM PST 24
Finished Jan 24 10:51:31 PM PST 24
Peak memory 239800 kb
Host smart-9fe683bd-b3b4-4b4f-988b-9a42f6cbc5ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611586511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.1611586511
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.826401796
Short name T271
Test name
Test status
Simulation time 297199131 ps
CPU time 3.87 seconds
Started Jan 24 09:07:07 PM PST 24
Finished Jan 24 09:07:11 PM PST 24
Peak memory 243564 kb
Host smart-08b90c27-19ad-4bde-b474-508b0ed83eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826401796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.826401796
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.3633486738
Short name T447
Test name
Test status
Simulation time 534153707 ps
CPU time 6.54 seconds
Started Jan 24 09:07:23 PM PST 24
Finished Jan 24 09:07:31 PM PST 24
Peak memory 244032 kb
Host smart-215c9bb8-0966-4f7b-91fb-d4d014929dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633486738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.3633486738
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.3764952335
Short name T471
Test name
Test status
Simulation time 2852017744 ps
CPU time 7.25 seconds
Started Jan 24 09:07:10 PM PST 24
Finished Jan 24 09:07:19 PM PST 24
Peak memory 247948 kb
Host smart-716ecb56-b6a7-4e05-8480-e16681b35e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764952335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.3764952335
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.3253939415
Short name T456
Test name
Test status
Simulation time 108952478 ps
CPU time 1.72 seconds
Started Jan 24 08:54:56 PM PST 24
Finished Jan 24 08:55:02 PM PST 24
Peak memory 239240 kb
Host smart-f5be3153-3bce-4c81-a7cc-83cfc74f284a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253939415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.3253939415
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.967367800
Short name T270
Test name
Test status
Simulation time 2507242696 ps
CPU time 4.5 seconds
Started Jan 24 09:06:36 PM PST 24
Finished Jan 24 09:06:41 PM PST 24
Peak memory 239644 kb
Host smart-d10d6c68-d0d5-4141-a763-ec22e0cbdc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967367800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.967367800
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.3246523490
Short name T68
Test name
Test status
Simulation time 801073651 ps
CPU time 5.48 seconds
Started Jan 24 08:54:54 PM PST 24
Finished Jan 24 08:55:03 PM PST 24
Peak memory 246152 kb
Host smart-69cb3f63-6d7d-4da6-9006-25c22bbbafd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3246523490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.3246523490
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.1566760566
Short name T574
Test name
Test status
Simulation time 316398034 ps
CPU time 4.93 seconds
Started Jan 24 09:08:25 PM PST 24
Finished Jan 24 09:08:31 PM PST 24
Peak memory 239612 kb
Host smart-3fad2555-4220-46a2-802d-ab478c572d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566760566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.1566760566
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.820810374
Short name T589
Test name
Test status
Simulation time 2014141428 ps
CPU time 6.56 seconds
Started Jan 24 09:07:48 PM PST 24
Finished Jan 24 09:07:55 PM PST 24
Peak memory 239404 kb
Host smart-297ac7df-ee37-4450-bf90-e7ad0d6afd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820810374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.820810374
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.2378031143
Short name T189
Test name
Test status
Simulation time 2442774530 ps
CPU time 4.86 seconds
Started Jan 24 09:07:49 PM PST 24
Finished Jan 24 09:07:56 PM PST 24
Peak memory 244264 kb
Host smart-62b823bc-2844-4405-9c46-20a0faa0309e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378031143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.2378031143
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.2441085924
Short name T664
Test name
Test status
Simulation time 401748061 ps
CPU time 3.14 seconds
Started Jan 24 09:07:52 PM PST 24
Finished Jan 24 09:07:56 PM PST 24
Peak memory 243644 kb
Host smart-1ff321a2-b40d-4fd4-b912-765630b1aff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441085924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.2441085924
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.499338625
Short name T485
Test name
Test status
Simulation time 413922167 ps
CPU time 4.31 seconds
Started Jan 24 09:18:07 PM PST 24
Finished Jan 24 09:18:13 PM PST 24
Peak memory 243708 kb
Host smart-ef0a90ce-92b9-4856-bb4e-9c0fa1b712a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499338625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.499338625
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.2618277582
Short name T310
Test name
Test status
Simulation time 223687756 ps
CPU time 5.73 seconds
Started Jan 24 09:08:19 PM PST 24
Finished Jan 24 09:08:27 PM PST 24
Peak memory 244392 kb
Host smart-c8bf524e-da64-4580-8f1c-313dfff0ec89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618277582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.2618277582
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.1687936148
Short name T166
Test name
Test status
Simulation time 524912414 ps
CPU time 4.42 seconds
Started Jan 24 09:08:18 PM PST 24
Finished Jan 24 09:08:24 PM PST 24
Peak memory 244256 kb
Host smart-6f838b0d-cc24-4992-bb38-b42f7bd55df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687936148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.1687936148
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.82307861
Short name T625
Test name
Test status
Simulation time 2073740512 ps
CPU time 7.08 seconds
Started Jan 24 09:08:18 PM PST 24
Finished Jan 24 09:08:27 PM PST 24
Peak memory 244844 kb
Host smart-bb68542d-bb56-446a-acf2-52858f41747b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82307861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.82307861
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.3277036255
Short name T250
Test name
Test status
Simulation time 149262133 ps
CPU time 2.77 seconds
Started Jan 24 09:38:43 PM PST 24
Finished Jan 24 09:38:46 PM PST 24
Peak memory 239520 kb
Host smart-142d6f86-01ee-4a53-9266-68a515b88c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277036255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.3277036255
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.2778969495
Short name T457
Test name
Test status
Simulation time 845060722 ps
CPU time 12.8 seconds
Started Jan 24 10:19:55 PM PST 24
Finished Jan 24 10:20:09 PM PST 24
Peak memory 247628 kb
Host smart-cc5db665-78d0-4663-8e2a-fde9e9089a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778969495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.2778969495
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.1903706399
Short name T519
Test name
Test status
Simulation time 160127371 ps
CPU time 4.25 seconds
Started Jan 25 03:40:05 AM PST 24
Finished Jan 25 03:40:10 AM PST 24
Peak memory 244676 kb
Host smart-58cd252b-9074-4dc6-a6ba-917d64ea6d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903706399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.1903706399
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.3546767201
Short name T684
Test name
Test status
Simulation time 1974799286 ps
CPU time 5.37 seconds
Started Jan 24 09:08:19 PM PST 24
Finished Jan 24 09:08:26 PM PST 24
Peak memory 243344 kb
Host smart-83bd2732-d85c-40d1-864f-98a285af2846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546767201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.3546767201
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.1196091791
Short name T194
Test name
Test status
Simulation time 190277936 ps
CPU time 5.37 seconds
Started Jan 24 09:08:18 PM PST 24
Finished Jan 24 09:08:25 PM PST 24
Peak memory 239532 kb
Host smart-89d88c09-b114-4545-ac0b-07cb7eb4bb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196091791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.1196091791
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.2818993948
Short name T331
Test name
Test status
Simulation time 93444441 ps
CPU time 2.19 seconds
Started Jan 24 08:55:19 PM PST 24
Finished Jan 24 08:55:22 PM PST 24
Peak memory 239968 kb
Host smart-313bd692-63c8-43b8-8174-39bf3202617a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818993948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.2818993948
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.4010669249
Short name T659
Test name
Test status
Simulation time 408559153 ps
CPU time 3.45 seconds
Started Jan 24 08:55:17 PM PST 24
Finished Jan 24 08:55:21 PM PST 24
Peak memory 244356 kb
Host smart-741ef8d5-01e8-4113-962b-ee578f236d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010669249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.4010669249
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.2861515410
Short name T653
Test name
Test status
Simulation time 503718157 ps
CPU time 7.02 seconds
Started Jan 24 08:55:18 PM PST 24
Finished Jan 24 08:55:26 PM PST 24
Peak memory 245468 kb
Host smart-b174e195-6171-4884-812b-a197490b880d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861515410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.2861515410
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.3071049475
Short name T6
Test name
Test status
Simulation time 472643582 ps
CPU time 6.82 seconds
Started Jan 24 08:55:19 PM PST 24
Finished Jan 24 08:55:27 PM PST 24
Peak memory 239664 kb
Host smart-84047a6c-63a4-45d4-838a-77737b4f1d11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3071049475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.3071049475
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.2041476577
Short name T336
Test name
Test status
Simulation time 648940487 ps
CPU time 4.47 seconds
Started Jan 24 08:55:18 PM PST 24
Finished Jan 24 08:55:23 PM PST 24
Peak memory 243236 kb
Host smart-1dd71388-43b2-4e25-b4d0-634f4450559c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041476577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.2041476577
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.3055353906
Short name T553
Test name
Test status
Simulation time 163005803 ps
CPU time 4.17 seconds
Started Jan 24 10:03:13 PM PST 24
Finished Jan 24 10:03:18 PM PST 24
Peak memory 243472 kb
Host smart-7fb0502a-e741-4c61-8225-421ddb714e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055353906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.3055353906
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.3587356928
Short name T484
Test name
Test status
Simulation time 140168393 ps
CPU time 3.65 seconds
Started Jan 24 09:08:19 PM PST 24
Finished Jan 24 09:08:24 PM PST 24
Peak memory 239468 kb
Host smart-682f85d2-64cf-4af3-81af-65e1384cd196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587356928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.3587356928
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.2998387474
Short name T498
Test name
Test status
Simulation time 184896168 ps
CPU time 4.31 seconds
Started Jan 24 09:08:36 PM PST 24
Finished Jan 24 09:08:41 PM PST 24
Peak memory 242936 kb
Host smart-321d1d62-1fe4-46eb-b04f-168089c0f993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998387474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.2998387474
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.3240498036
Short name T606
Test name
Test status
Simulation time 275395375 ps
CPU time 3.79 seconds
Started Jan 24 09:08:35 PM PST 24
Finished Jan 24 09:08:40 PM PST 24
Peak memory 244400 kb
Host smart-3adbe40a-57a1-4197-b368-4af89d5d7bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240498036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.3240498036
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.827070332
Short name T638
Test name
Test status
Simulation time 105029635 ps
CPU time 3.65 seconds
Started Jan 24 09:08:37 PM PST 24
Finished Jan 24 09:08:42 PM PST 24
Peak memory 242436 kb
Host smart-813f88c9-78b6-4779-829c-2bb8db5d3437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827070332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.827070332
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.1650058071
Short name T530
Test name
Test status
Simulation time 2246036682 ps
CPU time 6.46 seconds
Started Jan 24 09:08:38 PM PST 24
Finished Jan 24 09:08:46 PM PST 24
Peak memory 243636 kb
Host smart-07712b5a-40cc-47a2-ae3d-be8bc2944320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650058071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.1650058071
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.3086328549
Short name T460
Test name
Test status
Simulation time 199679051 ps
CPU time 6.08 seconds
Started Jan 24 09:08:38 PM PST 24
Finished Jan 24 09:08:46 PM PST 24
Peak memory 246260 kb
Host smart-55bf491d-29d2-4111-9f36-886719b573ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086328549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.3086328549
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.96234236
Short name T439
Test name
Test status
Simulation time 2233336234 ps
CPU time 5.85 seconds
Started Jan 24 09:08:39 PM PST 24
Finished Jan 24 09:08:47 PM PST 24
Peak memory 239296 kb
Host smart-7490ab97-dfcf-456c-acf5-105168da0f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96234236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.96234236
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.709609525
Short name T479
Test name
Test status
Simulation time 1289561010 ps
CPU time 3.37 seconds
Started Jan 24 09:08:39 PM PST 24
Finished Jan 24 09:08:45 PM PST 24
Peak memory 242536 kb
Host smart-9ce29d0b-7f4b-4e35-b485-f49050356300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709609525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.709609525
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.3446326493
Short name T326
Test name
Test status
Simulation time 555979306 ps
CPU time 4.13 seconds
Started Jan 24 09:08:39 PM PST 24
Finished Jan 24 09:08:45 PM PST 24
Peak memory 243964 kb
Host smart-3d04b1c6-14ec-408b-8cb9-f4800c572aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446326493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.3446326493
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.483197374
Short name T673
Test name
Test status
Simulation time 184900866 ps
CPU time 3.91 seconds
Started Jan 24 09:53:26 PM PST 24
Finished Jan 24 09:53:31 PM PST 24
Peak memory 243460 kb
Host smart-2413679e-84f4-4cbc-b005-e87575a0ee74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483197374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.483197374
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.4137993796
Short name T8
Test name
Test status
Simulation time 1517080225 ps
CPU time 10.21 seconds
Started Jan 24 09:08:40 PM PST 24
Finished Jan 24 09:08:52 PM PST 24
Peak memory 246704 kb
Host smart-95d3fedf-e662-430f-9b8b-499079271497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137993796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.4137993796
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.184443108
Short name T12
Test name
Test status
Simulation time 57455179 ps
CPU time 1.54 seconds
Started Jan 24 08:55:36 PM PST 24
Finished Jan 24 08:55:39 PM PST 24
Peak memory 239236 kb
Host smart-1f5e0cfc-5e07-4b7e-bdd7-2d9691dddbb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184443108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.184443108
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.3936598273
Short name T487
Test name
Test status
Simulation time 2421087883 ps
CPU time 6.38 seconds
Started Jan 24 09:40:05 PM PST 24
Finished Jan 24 09:40:12 PM PST 24
Peak memory 239644 kb
Host smart-74565a90-cb14-4a3e-b42a-770d03304478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936598273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.3936598273
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.4159121710
Short name T197
Test name
Test status
Simulation time 1787244286 ps
CPU time 3.41 seconds
Started Jan 24 08:55:36 PM PST 24
Finished Jan 24 08:55:42 PM PST 24
Peak memory 243512 kb
Host smart-bcd50571-9d5b-46b3-a696-24a3579e2b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159121710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.4159121710
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.1409064881
Short name T708
Test name
Test status
Simulation time 1095440522 ps
CPU time 8.34 seconds
Started Jan 24 08:55:34 PM PST 24
Finished Jan 24 08:55:44 PM PST 24
Peak memory 239632 kb
Host smart-8d683729-a62b-4132-9a4a-e04ea4de5b91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1409064881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.1409064881
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.3719911607
Short name T450
Test name
Test status
Simulation time 173872184 ps
CPU time 3.4 seconds
Started Jan 24 09:08:39 PM PST 24
Finished Jan 24 09:08:45 PM PST 24
Peak memory 244288 kb
Host smart-21cf7e80-04e9-44f1-9482-0b10474d7c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719911607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.3719911607
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.4082185947
Short name T327
Test name
Test status
Simulation time 386313208 ps
CPU time 3.03 seconds
Started Jan 24 10:24:25 PM PST 24
Finished Jan 24 10:24:29 PM PST 24
Peak memory 239508 kb
Host smart-55151f83-38e3-40c1-8c34-b713d5238df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082185947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.4082185947
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.1967759603
Short name T551
Test name
Test status
Simulation time 147769124 ps
CPU time 3.65 seconds
Started Jan 24 09:08:40 PM PST 24
Finished Jan 24 09:08:46 PM PST 24
Peak memory 243356 kb
Host smart-a437ba24-1f5f-418b-87ee-038835a491c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967759603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.1967759603
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.2247131008
Short name T253
Test name
Test status
Simulation time 1439525678 ps
CPU time 18.92 seconds
Started Jan 24 09:08:43 PM PST 24
Finished Jan 24 09:09:03 PM PST 24
Peak memory 239616 kb
Host smart-0a01d6eb-296a-4e58-aa5c-e323b95b2fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247131008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.2247131008
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.3746831779
Short name T274
Test name
Test status
Simulation time 2420636109 ps
CPU time 5.05 seconds
Started Jan 25 12:18:52 AM PST 24
Finished Jan 25 12:18:58 AM PST 24
Peak memory 242708 kb
Host smart-e58b993b-65d4-4e03-baf6-81dcbe7b8819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746831779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.3746831779
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.993751941
Short name T244
Test name
Test status
Simulation time 379991785 ps
CPU time 2.77 seconds
Started Jan 24 09:08:57 PM PST 24
Finished Jan 24 09:09:00 PM PST 24
Peak memory 243508 kb
Host smart-58dbb7b3-2009-4183-ad69-bacbf3ba9b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993751941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.993751941
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.3028920577
Short name T75
Test name
Test status
Simulation time 260918164 ps
CPU time 3.62 seconds
Started Jan 24 09:09:13 PM PST 24
Finished Jan 24 09:09:18 PM PST 24
Peak memory 243392 kb
Host smart-1b281bb3-73b9-4822-b982-e7aa5a335c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028920577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.3028920577
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.388523086
Short name T507
Test name
Test status
Simulation time 1734794439 ps
CPU time 4.96 seconds
Started Jan 24 09:09:14 PM PST 24
Finished Jan 24 09:09:20 PM PST 24
Peak memory 244204 kb
Host smart-8bebac49-7834-4d5c-9929-5ae1674e017b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388523086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.388523086
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.729445690
Short name T576
Test name
Test status
Simulation time 2947591581 ps
CPU time 5.24 seconds
Started Jan 24 09:08:56 PM PST 24
Finished Jan 24 09:09:02 PM PST 24
Peak memory 239668 kb
Host smart-9afebcdd-e09f-4c1c-9c1e-92d8e0e29499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729445690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.729445690
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.1672350022
Short name T560
Test name
Test status
Simulation time 2454929179 ps
CPU time 5.21 seconds
Started Jan 24 09:08:58 PM PST 24
Finished Jan 24 09:09:04 PM PST 24
Peak memory 245628 kb
Host smart-b2f8f8c1-eb66-4c44-aacd-2ad46dce5469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672350022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.1672350022
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.960045843
Short name T520
Test name
Test status
Simulation time 1711220914 ps
CPU time 5.26 seconds
Started Jan 24 09:48:55 PM PST 24
Finished Jan 24 09:49:04 PM PST 24
Peak memory 239512 kb
Host smart-0c3e321f-bc28-4d44-acdf-fb23ae33e0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960045843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.960045843
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.815225596
Short name T172
Test name
Test status
Simulation time 314551144 ps
CPU time 3.88 seconds
Started Jan 24 11:23:19 PM PST 24
Finished Jan 24 11:23:26 PM PST 24
Peak memory 242340 kb
Host smart-67303950-023d-4ab4-94e1-0d1539791445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815225596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.815225596
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.3826976100
Short name T674
Test name
Test status
Simulation time 139436099 ps
CPU time 4.45 seconds
Started Jan 24 09:44:41 PM PST 24
Finished Jan 24 09:44:46 PM PST 24
Peak memory 243444 kb
Host smart-8ab24310-a267-46e2-8420-0741b297ccd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826976100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.3826976100
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.3174332467
Short name T201
Test name
Test status
Simulation time 1608841039 ps
CPU time 10.04 seconds
Started Jan 24 09:09:13 PM PST 24
Finished Jan 24 09:09:24 PM PST 24
Peak memory 239412 kb
Host smart-d9ac913d-0d1d-43dd-9093-4b6c43baab1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174332467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.3174332467
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.2860599666
Short name T191
Test name
Test status
Simulation time 353106110 ps
CPU time 4.82 seconds
Started Jan 24 09:09:15 PM PST 24
Finished Jan 24 09:09:20 PM PST 24
Peak memory 239524 kb
Host smart-f1774168-6dd4-4c67-a389-3dce1880bfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860599666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.2860599666
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.562445251
Short name T682
Test name
Test status
Simulation time 601545324 ps
CPU time 1.92 seconds
Started Jan 24 08:56:06 PM PST 24
Finished Jan 24 08:56:09 PM PST 24
Peak memory 239620 kb
Host smart-a1500cdd-2687-408e-8d81-a614d5f83e5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562445251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.562445251
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.3114980954
Short name T174
Test name
Test status
Simulation time 628742791 ps
CPU time 4.23 seconds
Started Jan 24 08:55:36 PM PST 24
Finished Jan 24 08:55:42 PM PST 24
Peak memory 242516 kb
Host smart-8a2c5f23-ce53-4697-a15f-97ad22a8bb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114980954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.3114980954
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.2583217091
Short name T562
Test name
Test status
Simulation time 177846939 ps
CPU time 3.91 seconds
Started Jan 24 08:55:32 PM PST 24
Finished Jan 24 08:55:36 PM PST 24
Peak memory 244776 kb
Host smart-f5bc0857-b5f7-481b-b686-75bc5cc7e5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583217091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.2583217091
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.1871263217
Short name T567
Test name
Test status
Simulation time 230830036 ps
CPU time 5.11 seconds
Started Jan 24 09:09:42 PM PST 24
Finished Jan 24 09:09:48 PM PST 24
Peak memory 239536 kb
Host smart-da8b27f0-5eb4-4916-909a-9b66446df723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871263217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.1871263217
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.3221149014
Short name T259
Test name
Test status
Simulation time 344164385 ps
CPU time 4.77 seconds
Started Jan 24 09:09:41 PM PST 24
Finished Jan 24 09:09:47 PM PST 24
Peak memory 244584 kb
Host smart-40d6f552-bdb4-45a4-87c5-db2d027ec7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221149014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.3221149014
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.3066542914
Short name T654
Test name
Test status
Simulation time 112449978 ps
CPU time 3.59 seconds
Started Jan 24 09:09:39 PM PST 24
Finished Jan 24 09:09:43 PM PST 24
Peak memory 243360 kb
Host smart-646b70a5-0e4b-4441-a201-0512c27d3578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066542914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.3066542914
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.358005634
Short name T572
Test name
Test status
Simulation time 127519957 ps
CPU time 4.01 seconds
Started Jan 24 09:09:40 PM PST 24
Finished Jan 24 09:09:45 PM PST 24
Peak memory 239500 kb
Host smart-bea70199-1ff9-44f3-b41f-dacb576764de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358005634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.358005634
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.965395839
Short name T309
Test name
Test status
Simulation time 134805883 ps
CPU time 3.41 seconds
Started Jan 24 09:09:46 PM PST 24
Finished Jan 24 09:09:52 PM PST 24
Peak memory 243880 kb
Host smart-a63b1e0b-3f7c-4c81-be81-e349b4525f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965395839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.965395839
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.2740241705
Short name T78
Test name
Test status
Simulation time 114423033 ps
CPU time 3.82 seconds
Started Jan 24 09:09:45 PM PST 24
Finished Jan 24 09:09:52 PM PST 24
Peak memory 239524 kb
Host smart-08c0df33-0286-4407-9b09-f0b10a355437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740241705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.2740241705
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.976457866
Short name T54
Test name
Test status
Simulation time 380274574 ps
CPU time 3.53 seconds
Started Jan 24 09:09:42 PM PST 24
Finished Jan 24 09:09:47 PM PST 24
Peak memory 243680 kb
Host smart-453c8e4c-750b-450b-be22-d5e9710c394b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976457866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.976457866
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.63347560
Short name T46
Test name
Test status
Simulation time 134249387 ps
CPU time 3.32 seconds
Started Jan 24 09:10:33 PM PST 24
Finished Jan 24 09:10:44 PM PST 24
Peak memory 239508 kb
Host smart-4e720f09-d25e-4a53-8054-6df50314eaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63347560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.63347560
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.1263084355
Short name T617
Test name
Test status
Simulation time 2581734953 ps
CPU time 7.3 seconds
Started Jan 24 09:10:36 PM PST 24
Finished Jan 24 09:10:50 PM PST 24
Peak memory 243856 kb
Host smart-601f5385-32f2-4cfd-a963-660a8881a06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263084355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.1263084355
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.1213780768
Short name T591
Test name
Test status
Simulation time 134012396 ps
CPU time 2.14 seconds
Started Jan 24 09:10:28 PM PST 24
Finished Jan 24 09:10:34 PM PST 24
Peak memory 243656 kb
Host smart-f2daff30-f99e-4be4-bcc2-7ca6c3c563a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213780768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.1213780768
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.3612295128
Short name T619
Test name
Test status
Simulation time 668931729 ps
CPU time 1.76 seconds
Started Jan 24 08:56:20 PM PST 24
Finished Jan 24 08:56:23 PM PST 24
Peak memory 239052 kb
Host smart-f0d6c451-6e70-46a2-8cf7-8c3ff7472b9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612295128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.3612295128
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.2793899856
Short name T184
Test name
Test status
Simulation time 348192235 ps
CPU time 4.69 seconds
Started Jan 24 08:56:04 PM PST 24
Finished Jan 24 08:56:10 PM PST 24
Peak memory 243820 kb
Host smart-016da616-9213-4e53-a48e-fc30471b60d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793899856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.2793899856
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.2033290602
Short name T225
Test name
Test status
Simulation time 101366351 ps
CPU time 4.01 seconds
Started Jan 24 08:56:23 PM PST 24
Finished Jan 24 08:56:27 PM PST 24
Peak memory 239560 kb
Host smart-88f20114-96f1-4b30-a7cf-e0426845a8d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2033290602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.2033290602
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.1115931701
Short name T565
Test name
Test status
Simulation time 446561591 ps
CPU time 4.96 seconds
Started Jan 24 08:56:05 PM PST 24
Finished Jan 24 08:56:11 PM PST 24
Peak memory 239652 kb
Host smart-96e104ec-d549-4427-aed7-a8e5522173b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115931701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.1115931701
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.4148310468
Short name T596
Test name
Test status
Simulation time 163599967 ps
CPU time 3.98 seconds
Started Jan 24 09:10:34 PM PST 24
Finished Jan 24 09:10:47 PM PST 24
Peak memory 243880 kb
Host smart-a9ca6b2a-dbfc-4125-9aa6-6dd9624ea6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148310468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.4148310468
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.736814418
Short name T452
Test name
Test status
Simulation time 539343769 ps
CPU time 4.33 seconds
Started Jan 24 09:10:33 PM PST 24
Finished Jan 24 09:10:46 PM PST 24
Peak memory 242836 kb
Host smart-f353b9a4-9167-4c6b-aff9-7a4b610fcd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736814418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.736814418
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.454932353
Short name T260
Test name
Test status
Simulation time 3579769925 ps
CPU time 10.55 seconds
Started Jan 24 09:10:32 PM PST 24
Finished Jan 24 09:10:44 PM PST 24
Peak memory 247400 kb
Host smart-8c2e05d3-8dd8-4ae7-b34f-feda9a6c747b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454932353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.454932353
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.3807486079
Short name T714
Test name
Test status
Simulation time 550318829 ps
CPU time 4.21 seconds
Started Jan 24 09:10:33 PM PST 24
Finished Jan 24 09:10:44 PM PST 24
Peak memory 243460 kb
Host smart-13eeaf81-9740-4548-97e5-c83cf61d8522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807486079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.3807486079
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.716058585
Short name T311
Test name
Test status
Simulation time 149829061 ps
CPU time 7.68 seconds
Started Jan 24 09:10:36 PM PST 24
Finished Jan 24 09:10:50 PM PST 24
Peak memory 245468 kb
Host smart-c03f524a-779e-4473-86c2-9ff20bb3ff74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716058585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.716058585
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.3690217791
Short name T586
Test name
Test status
Simulation time 123097662 ps
CPU time 4.31 seconds
Started Jan 24 09:10:38 PM PST 24
Finished Jan 24 09:10:47 PM PST 24
Peak memory 244452 kb
Host smart-ecf97b50-2abe-41f3-a90d-82446c31c4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690217791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.3690217791
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.2667760903
Short name T258
Test name
Test status
Simulation time 121999046 ps
CPU time 4.72 seconds
Started Jan 24 10:02:04 PM PST 24
Finished Jan 24 10:02:09 PM PST 24
Peak memory 245436 kb
Host smart-130310a0-1439-419c-afa5-2c4d36d85f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667760903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.2667760903
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.2585890879
Short name T56
Test name
Test status
Simulation time 500020066 ps
CPU time 4.13 seconds
Started Jan 24 09:10:35 PM PST 24
Finished Jan 24 09:10:47 PM PST 24
Peak memory 239544 kb
Host smart-b0d9453f-d4cb-4186-b58d-8c91e0ea112e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585890879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.2585890879
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.724615526
Short name T198
Test name
Test status
Simulation time 384807791 ps
CPU time 5.3 seconds
Started Jan 24 09:10:34 PM PST 24
Finished Jan 24 09:10:48 PM PST 24
Peak memory 239504 kb
Host smart-cf53bed0-a610-4ad4-9840-01ac37174a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724615526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.724615526
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.3205818038
Short name T534
Test name
Test status
Simulation time 1814555073 ps
CPU time 4.07 seconds
Started Jan 24 09:10:35 PM PST 24
Finished Jan 24 09:10:47 PM PST 24
Peak memory 244068 kb
Host smart-4257d92a-e720-4a24-8704-343530b92cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205818038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.3205818038
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.707402767
Short name T489
Test name
Test status
Simulation time 613077276 ps
CPU time 4.21 seconds
Started Jan 24 09:10:59 PM PST 24
Finished Jan 24 09:11:06 PM PST 24
Peak memory 242600 kb
Host smart-77f8818d-ecf0-439d-a32f-6060a2a6934f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707402767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.707402767
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.1397228518
Short name T251
Test name
Test status
Simulation time 3786463348 ps
CPU time 7.03 seconds
Started Jan 24 09:11:00 PM PST 24
Finished Jan 24 09:11:11 PM PST 24
Peak memory 246624 kb
Host smart-3a6b86eb-02f2-497d-8be5-908fc0b81afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397228518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.1397228518
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.275886896
Short name T314
Test name
Test status
Simulation time 105638669 ps
CPU time 3.09 seconds
Started Jan 24 09:10:56 PM PST 24
Finished Jan 24 09:11:00 PM PST 24
Peak memory 244320 kb
Host smart-9643978d-d880-4511-b632-06f8730b9a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275886896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.275886896
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest
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