Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

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Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
secret1_lock	2	0	2	100.00	100	1	1	2
sram_index	4	0	4	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sram_req_lock_cross	8	0	8	100.00	100	1	1	0

Summary for Variable secret1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret1_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1703

1

T40

4

T5

23

T96

3

auto[1]

1469

1

T17

9

T40

8

T5

54

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Summary for Variable sram_index

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for sram_index

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_key[0x0]	118	1			T5	7		T6	3		T179	4
sram_key[0x1]	999	1			T17	3		T40	5		T5	30
sram_key[0x2]	1003	1			T17	3		T40	2		T5	9
sram_key[0x3]	1052	1			T17	3		T40	5		T5	31

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Summary for Cross sram_req_lock_cross

Samples crossed: sram_index secret1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for sram_req_lock_cross

Bins

sram_index	secret1_lock	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_key[0x0]	auto[0]	55	1			T5	2		T6	1		T179	1
sram_key[0x0]	auto[1]	63	1			T5	5		T6	2		T179	3
sram_key[0x1]	auto[0]	535	1			T40	2		T5	10		T96	1
sram_key[0x1]	auto[1]	464	1			T17	3		T40	3		T5	20
sram_key[0x2]	auto[0]	549	1			T5	1		T96	1		T99	4
sram_key[0x2]	auto[1]	454	1			T17	3		T40	2		T5	8
sram_key[0x3]	auto[0]	564	1			T40	2		T5	10		T96	1
sram_key[0x3]	auto[1]	488	1			T17	3		T40	3		T5	21