Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

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Summary for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
otbn_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
otbn_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
otbn_req_during_lc_esc	2	0	2	100.00	100	1	1	0
otbn_req_during_otp_idle	2	0	2	100.00	100	1	1	2
otbn_req_during_sram_0_req	2	0	2	100.00	100	1	1	2
otbn_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable otbn_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11862

1

T4

2

T5

89

T6

4

auto[1]

910

1

T5

7

T25

3

T12

1

---

Summary for Variable otbn_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11729

1

T4

2

T5

84

T6

4

auto[1]

1043

1

T5

12

T25

4

T12

2

---

Summary for Variable otbn_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for otbn_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

12751

1

T4

2

T5

96

T6

4

lc_esc_on

21

1

T243

1

T317

1

T400

1

---

Summary for Variable otbn_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2319

1

T5

13

T25

2

T11

3

auto[1]

10453

1

T4

2

T5

83

T6

4

---

Summary for Variable otbn_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11733

1

T4

2

T5

85

T6

4

auto[1]

1039

1

T5

11

T25

5

T12

2

---

Summary for Variable otbn_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12377

1

T4

2

T5

96

T6

4

auto[1]

395

1

T25

1

T12

1

T26

2