Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	47400	1			T3	142		T10	267		T113	18
access_err	60904	1			T1	22		T3	2		T4	3
write_blank_err	423	1			T1	8		T7	2		T5	11
ecc_uncorr_err	68497	1			T1	111		T7	246		T5	680
ecc_corr_err	1314	1			T1	1		T4	2		T5	3
no_err	88042	1			T1	47		T2	50		T3	19

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	592	1			T1	10		T7	4		T5	20
secret2	23821	1			T1	12		T2	1		T3	2
secret1	30128	1			T1	4		T2	4		T3	10
secret0	40226	1			T1	2		T2	4		T4	8
hw_cfg1	30866	1			T1	5		T2	11		T7	249
hw_cfg0	25464	1			T1	121		T2	3		T3	8
rot_creator_auth_state	21090	1			T1	12		T2	11		T3	1
rot_creator_auth_codesign	20954	1			T1	3		T2	3		T4	5
owner_sw_cfg	21886	1			T1	10		T2	9		T4	13
creator_sw_cfg	20202	1			T1	4		T2	2		T4	3
vendor_test	31351	1			T1	6		T2	2		T3	142

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3277	1			T10	267		T344	364		T345	134
fsm_err	secret1	5218	1			T114	312		T247	370		T203	17
fsm_err	secret0	3216	1			T191	31		T78	176		T268	653
fsm_err	hw_cfg1	2423	1			T165	469		T200	126		T249	109
fsm_err	hw_cfg0	4882	1			T149	251		T166	155		T242	382
fsm_err	rot_creator_auth_state	2562	1			T113	18		T37	257		T346	89
fsm_err	rot_creator_auth_codesign	3758	1			T347	16		T159	44		T292	67
fsm_err	owner_sw_cfg	4201	1			T230	109		T159	38		T160	10
fsm_err	creator_sw_cfg	3374	1			T37	284		T348	123		T289	1
fsm_err	vendor_test	14489	1			T3	142		T136	34		T29	6
access_err	life_cycle	592	1			T1	10		T7	4		T5	20
access_err	secret2	10991	1			T3	2		T5	104		T6	10
access_err	secret1	5981	1			T6	2		T25	13		T116	1
access_err	secret0	4916	1			T5	1		T6	2		T13	4
access_err	hw_cfg1	1280	1			T1	1		T5	5		T13	1
access_err	hw_cfg0	2086	1			T5	1		T13	5		T25	1
access_err	rot_creator_auth_state	5630	1			T7	1		T5	54		T13	11
access_err	rot_creator_auth_codesign	7505	1			T4	3		T7	4		T5	83
access_err	owner_sw_cfg	6798	1			T1	6		T7	7		T5	67
access_err	creator_sw_cfg	7986	1			T1	2		T7	1		T5	72
access_err	vendor_test	7139	1			T1	3		T5	64		T6	1
write_blank_err	secret2	14	1			T12	1		T290	1		T103	1
write_blank_err	secret1	23	1			T166	1		T78	1		T294	1
write_blank_err	secret0	48	1			T11	1		T12	1		T37	1
write_blank_err	hw_cfg1	56	1			T7	1		T5	2		T115	1
write_blank_err	hw_cfg0	23	1			T1	2		T343	1		T78	1
write_blank_err	rot_creator_auth_state	152	1			T1	4		T5	9		T11	5
write_blank_err	rot_creator_auth_codesign	64	1			T1	2		T7	1		T116	1
write_blank_err	owner_sw_cfg	15	1			T115	2		T12	2		T349	1
write_blank_err	creator_sw_cfg	6	1			T11	1		T350	1		T325	1
write_blank_err	vendor_test	22	1			T166	1		T103	2		T351	1
ecc_uncorr_err	secret2	4289	1			T8	33		T290	361		T204	48
ecc_uncorr_err	secret1	10133	1			T8	63		T166	322		T78	517
ecc_uncorr_err	secret0	23839	1			T8	18		T11	415		T12	601
ecc_uncorr_err	hw_cfg1	16545	1			T7	246		T5	230		T115	244
ecc_uncorr_err	hw_cfg0	5984	1			T1	111		T343	320		T159	54
ecc_uncorr_err	rot_creator_auth_state	4365	1			T5	450		T136	35		T204	44
ecc_uncorr_err	rot_creator_auth_codesign	798	1			T204	94		T352	36		T353	36
ecc_uncorr_err	owner_sw_cfg	1730	1			T8	40		T136	32		T160	12
ecc_uncorr_err	creator_sw_cfg	814	1			T204	27		T159	48		T203	26
ecc_corr_err	secret2	82	1			T12	3		T28	1		T39	3
ecc_corr_err	secret1	91	1			T4	1		T28	1		T63	1
ecc_corr_err	secret0	112	1			T28	5		T39	1		T85	1
ecc_corr_err	hw_cfg1	243	1			T5	3		T28	4		T39	21
ecc_corr_err	hw_cfg0	251	1			T1	1		T8	1		T28	7
ecc_corr_err	rot_creator_auth_state	147	1			T28	8		T39	14		T85	3
ecc_corr_err	rot_creator_auth_codesign	129	1			T28	7		T39	5		T85	2
ecc_corr_err	owner_sw_cfg	136	1			T4	1		T28	13		T39	8
ecc_corr_err	creator_sw_cfg	123	1			T28	2		T63	1		T39	12
no_err	secret2	5168	1			T1	12		T2	1		T4	2
no_err	secret1	8682	1			T1	4		T2	4		T3	10
no_err	secret0	8095	1			T1	2		T2	4		T4	8
no_err	hw_cfg1	10319	1			T1	4		T2	11		T7	2
no_err	hw_cfg0	12238	1			T1	7		T2	3		T3	8
no_err	rot_creator_auth_state	8234	1			T1	8		T2	11		T3	1
no_err	rot_creator_auth_codesign	8700	1			T1	1		T2	3		T4	2
no_err	owner_sw_cfg	9006	1			T1	4		T2	9		T4	12
no_err	creator_sw_cfg	7899	1			T1	2		T2	2		T4	3
no_err	vendor_test	9701	1			T1	3		T2	2		T4	2

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded