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Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 13720 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 13720 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 9814 1 T1 29 T2 3 T3 2
true 16078 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 10666 1 T1 35 T2 3 T3 3
true 16140 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 96 1 T99 2 T102 4 T179 2
others[1] 100 1 T98 2 T102 2 T178 2
others[2] 90 1 T93 2 T144 4 T260 2
others[3] 106 1 T4 2 T94 2 T97 2
others[4] 82 1 T100 2 T179 2 T202 2
others[5] 76 1 T144 2 T145 2 T368 2
others[6] 76 1 T1 2 T119 2 T142 2
others[7] 96 1 T97 2 T101 2 T142 2
false 13720 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T1 2 T102 2 T119 2
others[1] 84 1 T1 2 T178 2 T142 2
others[2] 70 1 T95 4 T100 2 T96 2
others[3] 84 1 T97 2 T99 2 T178 2
others[4] 96 1 T1 2 T22 2 T119 2
others[5] 82 1 T101 2 T144 2 T148 2
others[6] 80 1 T22 2 T93 2 T99 2
others[7] 94 1 T1 4 T96 2 T369 2
false 13720 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 76 1 T97 2 T142 2 T370 2
others[1] 84 1 T40 2 T93 2 T94 2
others[2] 106 1 T94 2 T102 2 T371 2
others[3] 94 1 T1 2 T40 2 T95 2
others[4] 58 1 T142 2 T372 2 T209 2
others[5] 96 1 T1 2 T102 2 T178 2
others[6] 106 1 T181 2 T142 2 T144 2
others[7] 104 1 T65 2 T111 2 T144 2
false 13720 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 66 1 T102 2 T373 2 T202 2
others[1] 66 1 T1 2 T40 2 T94 2
others[2] 76 1 T94 2 T100 2 T371 2
others[3] 54 1 T1 2 T144 2 T370 2
others[4] 44 1 T96 2 T102 2 T121 2
others[5] 78 1 T40 2 T100 2 T98 4
others[6] 58 1 T1 2 T89 2 T102 2
others[7] 82 1 T1 2 T102 2 T180 2
false 13720 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T1 2 T22 2 T98 2
others[1] 96 1 T40 2 T102 2 T202 2
others[2] 108 1 T4 2 T100 2 T119 2
others[3] 84 1 T1 2 T98 2 T119 2
others[4] 68 1 T1 2 T177 2 T371 2
others[5] 88 1 T1 2 T93 4 T94 2
others[6] 82 1 T22 2 T144 2 T260 2
others[7] 108 1 T371 2 T142 2 T374 4
false 13720 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 46 1 T93 2 T181 2 T142 2
others[1] 40 1 T98 2 T111 2 T142 2
others[2] 34 1 T93 2 T144 2 T254 2
others[3] 40 1 T116 2 T375 2 T217 2
others[4] 38 1 T142 2 T145 2 T154 2
others[5] 32 1 T376 2 T320 2 T377 2
others[6] 40 1 T209 2 T210 2 T154 2
others[7] 36 1 T179 2 T144 2 T259 2
false 13720 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 62 1 T94 2 T99 2 T378 2
others[1] 62 1 T40 2 T98 2 T202 2
others[2] 88 1 T40 2 T95 2 T101 2
others[3] 110 1 T1 2 T97 2 T101 2
others[4] 84 1 T1 2 T102 2 T371 2
others[5] 90 1 T1 2 T22 2 T40 2
others[6] 94 1 T4 2 T95 2 T102 2
others[7] 116 1 T65 2 T102 2 T74 2
false 13720 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T4 2 T23 2 T94 2
others[1] 46 1 T209 2 T262 2 T379 2
others[2] 88 1 T93 2 T111 2 T179 2
others[3] 84 1 T1 2 T374 2 T370 2
others[4] 86 1 T1 2 T94 2 T371 2
others[5] 88 1 T101 2 T119 2 T371 2
others[6] 78 1 T23 2 T40 2 T119 2
others[7] 110 1 T93 2 T102 2 T370 8
false 13720 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T65 2 T93 2 T97 2
others[1] 112 1 T1 2 T71 2 T74 2
others[2] 76 1 T380 2 T370 4 T381 4
others[3] 68 1 T96 2 T98 2 T101 2
others[4] 94 1 T101 2 T119 2 T111 2
others[5] 72 1 T97 2 T74 2 T142 4
others[6] 102 1 T1 2 T142 4 T209 2
others[7] 100 1 T40 2 T99 2 T102 2
false 13720 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T96 2 T101 2 T102 4
others[1] 92 1 T93 2 T94 2 T178 2
others[2] 102 1 T1 2 T95 4 T71 2
others[3] 72 1 T97 2 T373 2 T142 2
others[4] 76 1 T40 2 T93 2 T71 2
others[5] 84 1 T89 2 T99 2 T380 2
others[6] 72 1 T1 2 T98 2 T56 2
others[7] 84 1 T1 2 T144 4 T260 4
false 13720 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 86 1 T1 4 T102 2 T74 2
others[1] 80 1 T98 2 T178 2 T142 2
others[2] 92 1 T93 2 T99 2 T102 2
others[3] 106 1 T139 2 T370 2 T77 2
others[4] 70 1 T178 2 T74 2 T144 2
others[5] 84 1 T4 4 T93 2 T99 2
others[6] 84 1 T1 2 T181 2 T144 2
others[7] 98 1 T1 4 T97 2 T102 2
false 13720 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 26 1 T7 1 T129 1 T33 1
others[1] 34 1 T177 2 T15 1 T119 2
others[2] 35 1 T6 1 T7 1 T130 1
others[3] 21 1 T6 1 T119 2 T129 1
others[4] 30 1 T6 2 T15 1 T130 3
others[5] 38 1 T6 2 T96 2 T15 2
others[6] 36 1 T6 1 T7 1 T33 1
others[7] 23 1 T6 2 T240 1 T232 1
false 13720 1 T1 46 T2 3 T3 4
true 2233 1 T1 11 T4 4 T5 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 42 1 T6 2 T96 2 T15 1
others[1] 20 1 T15 1 T119 2 T129 1
others[2] 18 1 T7 1 T200 1 T232 1
others[3] 36 1 T7 1 T119 2 T33 2
others[4] 27 1 T130 1 T144 2 T274 1
others[5] 26 1 T6 2 T7 1 T130 2
others[6] 44 1 T6 3 T15 1 T130 1
others[7] 31 1 T6 2 T177 2 T15 1
false 11159 1 T1 38 T2 3 T3 3
true 18317 1 T1 57 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 104 1 T93 2 T119 2 T142 4
others[1] 96 1 T97 2 T99 2 T102 2
others[2] 90 1 T1 2 T100 2 T102 2
others[3] 94 1 T97 2 T179 2 T202 2
others[4] 90 1 T98 2 T74 2 T144 2
others[5] 78 1 T4 2 T101 2 T142 2
others[6] 80 1 T98 2 T102 2 T178 2
others[7] 90 1 T94 2 T102 2 T371 2
false 7442 1 T1 6 T2 3 T3 1
true 16180 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 76 1 T1 2 T96 2 T97 2
others[1] 80 1 T93 2 T178 2 T74 2
others[2] 90 1 T1 2 T22 2 T178 2
others[3] 54 1 T1 2 T95 2 T370 2
others[4] 84 1 T1 4 T100 2 T144 2
others[5] 96 1 T22 2 T369 2 T142 2
others[6] 78 1 T96 2 T145 2 T260 2
others[7] 116 1 T95 2 T99 4 T101 2
false 6600 1 T1 12 T2 3 T3 1
true 15947 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 98 1 T65 2 T93 2 T142 2
others[1] 100 1 T95 2 T102 2 T111 2
others[2] 104 1 T102 2 T144 2 T209 2
others[3] 78 1 T97 2 T102 2 T144 2
others[4] 76 1 T40 2 T142 2 T144 2
others[5] 94 1 T1 4 T111 2 T144 2
others[6] 82 1 T94 2 T98 2 T102 2
others[7] 92 1 T40 2 T94 2 T142 2
false 7081 1 T1 11 T2 2 T3 1
true 15974 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 42 1 T33 2 T130 1 T373 2
others[1] 27 1 T7 1 T15 1 T130 1
others[2] 18 1 T6 1 T130 1 T120 1
others[3] 28 1 T129 1 T382 2 T252 2
others[4] 31 1 T130 1 T200 1 T240 1
others[5] 25 1 T6 1 T7 1 T15 1
others[6] 27 1 T373 2 T232 1 T383 2
others[7] 20 1 T6 1 T15 1 T274 1
false 11095 1 T1 38 T2 3 T3 3
true 18245 1 T1 61 T2 3 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 58 1 T1 2 T89 2 T98 2
others[1] 58 1 T40 2 T94 2 T98 2
others[2] 58 1 T1 2 T94 2 T371 2
others[3] 70 1 T40 2 T96 2 T180 2
others[4] 64 1 T1 2 T100 4 T102 2
others[5] 58 1 T74 2 T373 2 T371 2
others[6] 68 1 T101 2 T102 2 T202 2
others[7] 90 1 T1 2 T102 4 T121 2
false 8639 1 T1 6 T2 3 T3 3
true 16170 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 27 1 T6 1 T200 1 T215 1
others[1] 30 1 T6 1 T102 2 T15 1
others[2] 26 1 T6 1 T7 1 T15 1
others[3] 35 1 T129 1 T200 1 T142 2
others[4] 21 1 T6 2 T130 1 T121 2
others[5] 18 1 T6 1 T33 1 T130 1
others[6] 44 1 T15 1 T119 2 T202 2
others[7] 18 1 T65 2 T6 1 T7 1
false 11043 1 T1 38 T2 3 T3 3
true 18250 1 T1 59 T2 3 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 86 1 T119 2 T371 2 T202 2
others[1] 86 1 T1 2 T4 2 T93 2
others[2] 98 1 T1 4 T102 2 T371 2
others[3] 88 1 T1 2 T371 2 T384 2
others[4] 98 1 T22 2 T40 2 T100 2
others[5] 86 1 T98 2 T102 2 T260 2
others[6] 74 1 T22 2 T93 2 T98 2
others[7] 108 1 T94 2 T119 2 T144 2
false 7381 1 T1 6 T2 3 T3 1
true 16093 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 32 1 T6 1 T15 1 T129 1
others[1] 17 1 T6 1 T7 1 T129 1
others[2] 21 1 T15 1 T130 1 T232 1
others[3] 31 1 T129 1 T33 1 T142 2
others[4] 34 1 T6 1 T7 1 T33 1
others[5] 25 1 T232 1 T211 1 T213 1
others[6] 25 1 T240 1 T232 1 T211 1
others[7] 21 1 T120 1 T253 2 T277 1
false 10998 1 T1 38 T2 3 T3 3
true 18211 1 T1 60 T2 3 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 44 1 T181 2 T370 2 T154 2
others[1] 32 1 T98 2 T142 2 T385 2
others[2] 38 1 T93 2 T142 2 T144 2
others[3] 32 1 T142 2 T144 2 T155 2
others[4] 40 1 T144 2 T145 2 T116 2
others[5] 38 1 T93 2 T111 2 T209 2
others[6] 34 1 T179 2 T145 2 T116 2
others[7] 48 1 T209 4 T370 2 T154 2
false 9473 1 T1 38 T2 3 T3 1
true 16153 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 120 1 T1 2 T65 2 T40 2
others[1] 86 1 T4 2 T145 2 T378 2
others[2] 90 1 T22 2 T40 2 T102 2
others[3] 82 1 T40 2 T99 2 T101 2
others[4] 76 1 T95 2 T102 2 T179 2
others[5] 68 1 T101 2 T119 2 T74 4
others[6] 84 1 T97 2 T99 2 T142 2
others[7] 100 1 T1 4 T98 2 T102 2
false 6695 1 T1 11 T2 2 T3 2
true 15951 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 74 1 T23 2 T94 2 T97 2
others[1] 86 1 T93 4 T102 2 T374 2
others[2] 80 1 T4 2 T111 2 T144 4
others[3] 76 1 T1 2 T97 2 T101 2
others[4] 84 1 T23 2 T40 2 T119 2
others[5] 96 1 T371 2 T262 2 T370 6
others[6] 52 1 T370 2 T121 2 T222 2
others[7] 116 1 T1 2 T94 2 T119 2
false 6695 1 T1 11 T2 2 T3 2
true 15951 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 112 1 T71 2 T101 2 T119 2
others[1] 70 1 T142 4 T144 4 T386 2
others[2] 92 1 T98 2 T178 2 T74 2
others[3] 98 1 T1 2 T93 2 T56 2
others[4] 70 1 T102 2 T387 2 T388 2
others[5] 76 1 T96 2 T74 2 T144 2
others[6] 108 1 T1 2 T97 2 T251 2
others[7] 88 1 T65 2 T40 2 T97 2
false 6139 1 T1 10 T2 1 T3 1
true 15957 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 64 1 T71 2 T96 2 T101 2
others[1] 72 1 T1 2 T40 2 T102 2
others[2] 86 1 T93 2 T98 2 T102 2
others[3] 74 1 T74 2 T142 2 T368 2
others[4] 94 1 T1 2 T89 2 T95 2
others[5] 84 1 T95 2 T71 2 T101 2
others[6] 96 1 T97 2 T99 2 T56 2
others[7] 96 1 T1 2 T93 2 T94 2
false 6139 1 T1 10 T2 1 T3 1
true 15957 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 74 1 T101 2 T144 4 T370 6
others[1] 70 1 T22 2 T94 2 T142 2
others[2] 72 1 T142 2 T144 4 T389 2
others[3] 54 1 T40 2 T96 2 T98 2
others[4] 62 1 T98 2 T180 2 T144 2
others[5] 72 1 T97 2 T101 2 T181 2
others[6] 76 1 T1 2 T102 2 T260 2
others[7] 60 1 T101 2 T369 2 T387 2
false 6616 1 T1 14 T2 1 T3 1
true 17295 1 T1 54 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 54 1 T1 2 T101 2 T142 2
others[1] 48 1 T94 2 T144 4 T209 2
others[2] 60 1 T97 2 T371 2 T145 2
others[3] 62 1 T373 2 T142 2 T77 2
others[4] 58 1 T366 2 T370 2 T77 2
others[5] 70 1 T102 2 T179 2 T180 2
others[6] 50 1 T94 2 T96 2 T181 2
others[7] 76 1 T22 2 T180 2 T144 2
false 6616 1 T1 14 T2 1 T3 1
true 17295 1 T1 54 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 37 1 T33 1 T130 1 T138 2
others[1] 35 1 T15 1 T129 1 T111 2
others[2] 32 1 T6 1 T215 1 T273 1
others[3] 22 1 T6 1 T15 1 T33 1
others[4] 25 1 T1 2 T6 1 T130 1
others[5] 20 1 T232 1 T253 1 T313 1
others[6] 33 1 T6 1 T330 2 T232 1
others[7] 39 1 T6 1 T7 2 T15 2
false 11239 1 T1 38 T2 3 T3 3
true 18400 1 T1 60 T2 3 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 82 1 T102 2 T74 2 T371 2
others[1] 106 1 T1 2 T93 2 T102 2
others[2] 84 1 T99 2 T74 2 T181 2
others[3] 86 1 T1 2 T102 2 T384 2
others[4] 76 1 T1 2 T98 2 T181 2
others[5] 92 1 T99 2 T142 2 T144 2
others[6] 92 1 T1 4 T4 2 T93 2
others[7] 82 1 T4 2 T262 2 T370 2
false 7420 1 T1 6 T2 3 T3 1
true 16154 1 T1 46 T2 3 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 28 1 T33 1 T200 1 T240 1
others[1] 19 1 T6 2 T15 1 T130 1
others[2] 17 1 T6 1 T129 1 T373 2
others[3] 29 1 T130 1 T200 1 T253 1
others[4] 19 1 T7 1 T33 1 T200 1
others[5] 30 1 T7 1 T33 1 T130 3
others[6] 39 1 T15 1 T130 1 T373 2
others[7] 37 1 T15 1 T213 1 T274 2
false 13720 1 T1 46 T2 3 T3 4
true 2196 1 T1 15 T3 1 T4 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%