Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
flash_data_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
flash_data_req_during_lc_esc	2	0	2	100.00	100	1	1	0
flash_data_req_during_otbn_req	2	0	2	100.00	100	1	1	2
flash_data_req_during_otp_idle	2	0	2	100.00	100	1	1	2
flash_data_req_during_sram_0_req	2	0	2	100.00	100	1	1	2
flash_data_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable flash_data_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11097

1

T1

49

T4

8

T5

8

auto[1]

805

1

T1

5

T22

2

T6

17

---

Summary for Variable flash_data_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for flash_data_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

11875

1

T1

54

T4

8

T5

8

lc_esc_on

27

1

T74

1

T330

1

T390

1

---

Summary for Variable flash_data_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11143

1

T1

45

T4

8

T5

8

auto[1]

759

1

T1

9

T22

1

T6

13

---

Summary for Variable flash_data_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1728

1

T1

19

T22

5

T6

15

auto[1]

10174

1

T1

35

T4

8

T5

8

---

Summary for Variable flash_data_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9880

1

T1

48

T4

4

T5

8

auto[1]

2022

1

T1

6

T4

4

T22

2

---

Summary for Variable flash_data_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11587

1

T1

51

T4

8

T5

8

auto[1]

315

1

T1

3

T93

12

T94

6