Summary for Variable dai_access_cmd
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for dai_access_cmd
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
dai_digest |
2149 |
1 |
|
|
T1 |
11 |
|
T2 |
1 |
|
T3 |
1 |
dai_wr |
4010 |
1 |
|
|
T1 |
9 |
|
T2 |
1 |
|
T3 |
2 |
dai_rd |
6907 |
1 |
|
|
T1 |
15 |
|
T2 |
3 |
|
T3 |
1 |
Summary for Variable lc_creator_seed_sw_rw_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_creator_seed_sw_rw_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5756 |
1 |
|
|
T1 |
23 |
|
T9 |
2 |
|
T4 |
10 |
auto[1] |
7310 |
1 |
|
|
T1 |
12 |
|
T2 |
5 |
|
T3 |
4 |
Summary for Cross dai_access_secret2
Samples crossed: lc_creator_seed_sw_rw_en dai_access_cmd
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins for dai_access_secret2
Bins
lc_creator_seed_sw_rw_en | dai_access_cmd | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
dai_digest |
1151 |
1 |
|
|
T1 |
7 |
|
T4 |
1 |
|
T65 |
2 |
auto[0] |
dai_wr |
1457 |
1 |
|
|
T1 |
5 |
|
T9 |
1 |
|
T4 |
3 |
auto[0] |
dai_rd |
3148 |
1 |
|
|
T1 |
11 |
|
T9 |
1 |
|
T4 |
6 |
auto[1] |
dai_digest |
998 |
1 |
|
|
T1 |
4 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
dai_wr |
2553 |
1 |
|
|
T1 |
4 |
|
T2 |
1 |
|
T3 |
2 |
auto[1] |
dai_rd |
3759 |
1 |
|
|
T1 |
4 |
|
T2 |
3 |
|
T3 |
1 |