Summary for Variable keymgr_rd_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for keymgr_rd_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3535 |
1 |
|
|
T1 |
17 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
2423 |
1 |
|
|
T1 |
8 |
|
T9 |
1 |
|
T4 |
2 |
Summary for Variable secret2_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for secret2_lock
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4131 |
1 |
|
|
T1 |
14 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
1827 |
1 |
|
|
T1 |
11 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Cross keymgr_output_conditions
Samples crossed: keymgr_rd_en secret2_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for keymgr_output_conditions
Bins
keymgr_rd_en | secret2_lock | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
2459 |
1 |
|
|
T1 |
10 |
|
T2 |
1 |
|
T3 |
1 |
auto[0] |
auto[1] |
1076 |
1 |
|
|
T1 |
7 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
auto[0] |
1672 |
1 |
|
|
T1 |
4 |
|
T9 |
1 |
|
T4 |
1 |
auto[1] |
auto[1] |
751 |
1 |
|
|
T1 |
4 |
|
T4 |
1 |
|
T23 |
3 |