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Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 13822 1 T1 25 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 13822 1 T1 25 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 9847 1 T1 18 T2 2 T3 2
true 16183 1 T1 34 T2 5 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 10764 1 T1 21 T2 3 T3 2
true 16245 1 T1 34 T2 5 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 96 1 T96 2 T97 2 T176 2
others[1] 96 1 T13 2 T75 2 T212 2
others[2] 102 1 T5 2 T96 4 T176 2
others[3] 104 1 T62 2 T111 2 T70 2
others[4] 78 1 T52 2 T96 2 T91 2
others[5] 106 1 T5 2 T128 2 T70 2
others[6] 72 1 T98 2 T128 2 T70 2
others[7] 120 1 T31 2 T212 2 T380 2
false 13822 1 T1 25 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 88 1 T13 2 T62 2 T96 2
others[1] 108 1 T5 2 T96 4 T70 2
others[2] 70 1 T100 2 T67 2 T248 2
others[3] 90 1 T4 2 T52 2 T31 2
others[4] 90 1 T13 2 T31 2 T96 2
others[5] 60 1 T13 2 T96 2 T248 2
others[6] 98 1 T177 2 T178 2 T70 4
others[7] 116 1 T31 2 T96 4 T99 2
false 13822 1 T1 25 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 70 1 T111 2 T181 4 T123 2
others[1] 86 1 T13 2 T31 2 T96 4
others[2] 86 1 T100 4 T178 2 T75 2
others[3] 74 1 T13 2 T67 4 T381 2
others[4] 64 1 T96 2 T178 2 T382 2
others[5] 102 1 T101 2 T263 2 T181 2
others[6] 94 1 T62 2 T100 2 T110 2
others[7] 140 1 T100 2 T110 2 T111 2
false 13822 1 T1 25 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 58 1 T31 2 T55 2 T176 2
others[1] 52 1 T31 2 T55 2 T178 2
others[2] 74 1 T100 4 T178 2 T67 2
others[3] 42 1 T383 2 T288 2 T384 4
others[4] 54 1 T91 2 T70 2 T248 2
others[5] 52 1 T62 2 T96 2 T248 2
others[6] 74 1 T98 4 T91 2 T181 2
others[7] 66 1 T70 4 T181 4 T385 2
false 13822 1 T1 25 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 104 1 T13 2 T62 2 T101 2
others[1] 92 1 T31 2 T110 4 T70 2
others[2] 114 1 T62 2 T90 2 T128 4
others[3] 90 1 T98 2 T70 2 T123 8
others[4] 104 1 T143 2 T110 2 T177 2
others[5] 84 1 T96 2 T177 2 T178 2
others[6] 66 1 T110 2 T111 2 T112 2
others[7] 102 1 T96 2 T98 2 T176 2
false 13822 1 T1 25 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 36 1 T90 2 T212 2 T254 2
others[1] 40 1 T121 2 T386 2 T181 2
others[2] 48 1 T111 2 T177 2 T380 2
others[3] 38 1 T96 2 T177 2 T212 2
others[4] 48 1 T13 2 T62 2 T96 2
others[5] 38 1 T177 2 T213 2 T384 4
others[6] 40 1 T70 4 T248 2 T288 2
others[7] 32 1 T96 2 T128 2 T111 2
false 13822 1 T1 25 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 86 1 T62 2 T178 2 T70 4
others[1] 100 1 T31 2 T110 2 T70 2
others[2] 78 1 T13 2 T70 4 T123 2
others[3] 60 1 T13 2 T52 2 T31 2
others[4] 92 1 T98 2 T91 2 T100 2
others[5] 82 1 T62 2 T96 4 T165 2
others[6] 92 1 T99 2 T121 2 T263 2
others[7] 120 1 T96 2 T100 2 T101 2
false 13822 1 T1 25 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 74 1 T96 2 T99 2 T100 2
others[1] 82 1 T90 2 T111 2 T385 2
others[2] 102 1 T5 2 T31 2 T62 2
others[3] 102 1 T5 2 T62 4 T96 2
others[4] 88 1 T12 2 T96 4 T98 2
others[5] 84 1 T31 2 T97 2 T70 4
others[6] 82 1 T4 2 T13 2 T110 2
others[7] 100 1 T62 2 T101 4 T177 2
false 13822 1 T1 25 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 96 1 T96 2 T128 2 T112 2
others[1] 78 1 T13 2 T52 2 T31 2
others[2] 100 1 T5 2 T95 2 T96 6
others[3] 78 1 T96 2 T70 2 T181 4
others[4] 76 1 T177 2 T181 4 T387 4
others[5] 106 1 T5 2 T128 2 T177 2
others[6] 78 1 T111 2 T177 2 T248 2
others[7] 92 1 T5 2 T90 2 T100 2
false 13822 1 T1 25 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T96 2 T128 2 T70 2
others[1] 90 1 T5 2 T96 4 T99 2
others[2] 82 1 T70 4 T181 4 T388 2
others[3] 86 1 T55 2 T91 2 T128 2
others[4] 88 1 T96 2 T263 2 T380 2
others[5] 86 1 T96 2 T97 4 T91 2
others[6] 90 1 T62 2 T110 2 T112 2
others[7] 92 1 T13 4 T31 2 T96 2
false 13822 1 T1 25 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 110 1 T5 2 T100 2 T110 2
others[1] 94 1 T62 2 T389 2 T181 4
others[2] 100 1 T96 2 T91 2 T101 2
others[3] 100 1 T96 2 T97 2 T110 2
others[4] 86 1 T62 4 T100 2 T110 2
others[5] 112 1 T75 2 T212 2 T70 8
others[6] 70 1 T96 2 T97 2 T177 2
others[7] 98 1 T52 2 T97 2 T212 2
false 13822 1 T1 25 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 37 1 T96 2 T121 2 T67 2
others[1] 31 1 T178 2 T247 2 T116 2
others[2] 26 1 T30 1 T131 2 T181 2
others[3] 22 1 T247 1 T219 1 T260 1
others[4] 33 1 T7 1 T8 1 T14 1
others[5] 20 1 T7 1 T30 1 T131 1
others[6] 30 1 T218 1 T271 2 T284 1
others[7] 29 1 T7 1 T30 1 T122 1
false 13822 1 T1 25 T2 5 T3 3
true 2205 1 T1 1 T4 1 T11 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 22 1 T121 2 T178 2 T219 1
others[1] 32 1 T14 1 T218 1 T247 1
others[2] 28 1 T131 1 T247 2 T248 2
others[3] 19 1 T7 1 T218 1 T271 1
others[4] 28 1 T30 1 T67 2 T271 1
others[5] 32 1 T96 2 T7 1 T122 1
others[6] 35 1 T8 1 T30 1 T131 2
others[7] 32 1 T7 1 T30 2 T181 2
false 11204 1 T1 21 T2 4 T3 2
true 18434 1 T1 34 T2 6 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T52 2 T176 2 T121 2
others[1] 78 1 T96 4 T212 2 T70 4
others[2] 80 1 T97 2 T128 2 T75 2
others[3] 104 1 T62 2 T70 2 T181 6
others[4] 98 1 T31 2 T91 4 T177 2
others[5] 104 1 T128 2 T111 2 T75 2
others[6] 88 1 T98 2 T181 2 T248 2
others[7] 138 1 T5 4 T13 2 T96 4
false 7556 1 T1 21 T2 4 T3 2
true 16289 1 T1 34 T2 6 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 80 1 T5 2 T13 2 T178 2
others[1] 84 1 T31 2 T70 2 T389 2
others[2] 90 1 T96 8 T99 2 T110 2
others[3] 112 1 T31 2 T97 2 T101 2
others[4] 76 1 T13 4 T52 2 T62 2
others[5] 70 1 T31 2 T96 4 T100 4
others[6] 94 1 T4 2 T70 2 T389 2
others[7] 114 1 T96 2 T177 2 T178 2
false 6594 1 T1 18 T2 2 T3 2
true 16059 1 T1 34 T2 5 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T96 2 T178 2 T70 6
others[1] 76 1 T13 2 T96 2 T100 2
others[2] 96 1 T13 2 T111 2 T70 4
others[3] 94 1 T62 2 T110 2 T178 4
others[4] 86 1 T100 2 T101 2 T110 2
others[5] 80 1 T100 4 T111 2 T121 2
others[6] 90 1 T96 2 T111 2 T177 2
others[7] 104 1 T31 2 T112 2 T177 2
false 7118 1 T1 21 T2 3 T3 2
true 16079 1 T1 34 T2 5 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 27 1 T247 1 T219 1 T338 1
others[1] 27 1 T242 2 T101 2 T30 1
others[2] 19 1 T7 2 T131 1 T218 1
others[3] 32 1 T30 3 T218 1 T247 1
others[4] 33 1 T96 2 T177 2 T165 2
others[5] 27 1 T30 1 T131 2 T285 2
others[6] 21 1 T30 1 T70 2 T381 2
others[7] 41 1 T99 2 T382 2 T263 2
false 11144 1 T1 21 T2 3 T3 2
true 18320 1 T1 34 T2 5 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 58 1 T31 2 T248 2 T390 2
others[1] 48 1 T91 2 T288 2 T149 2
others[2] 52 1 T55 2 T70 2 T263 2
others[3] 64 1 T98 2 T100 4 T70 2
others[4] 60 1 T96 2 T178 2 T181 2
others[5] 40 1 T31 2 T91 2 T177 2
others[6] 66 1 T62 2 T98 2 T178 2
others[7] 84 1 T55 2 T176 2 T389 2
false 8756 1 T1 21 T2 3 T3 2
true 16293 1 T1 34 T2 5 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 22 1 T30 1 T219 1 T260 1
others[1] 30 1 T7 2 T30 1 T382 2
others[2] 28 1 T96 2 T8 1 T14 1
others[3] 26 1 T7 1 T8 1 T14 1
others[4] 28 1 T7 1 T280 1 T131 1
others[5] 22 1 T7 1 T14 1 T30 1
others[6] 37 1 T8 1 T131 1 T150 2
others[7] 29 1 T7 1 T131 1 T122 1
false 11091 1 T1 21 T2 3 T3 2
true 18289 1 T1 34 T2 5 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 72 1 T98 2 T90 2 T100 2
others[1] 98 1 T31 2 T62 2 T176 2
others[2] 102 1 T143 2 T100 2 T110 2
others[3] 90 1 T96 4 T101 2 T121 2
others[4] 96 1 T62 2 T100 2 T128 2
others[5] 82 1 T98 2 T128 2 T111 2
others[6] 86 1 T110 2 T111 2 T75 2
others[7] 130 1 T13 2 T128 2 T110 2
false 7487 1 T1 21 T2 3 T3 2
true 16204 1 T1 34 T2 5 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 26 1 T96 2 T30 2 T75 2
others[1] 34 1 T7 1 T14 1 T131 1
others[2] 30 1 T7 1 T131 1 T219 1
others[3] 35 1 T7 1 T177 2 T14 1
others[4] 28 1 T7 1 T122 1 T380 2
others[5] 23 1 T181 2 T219 2 T285 1
others[6] 27 1 T165 2 T218 1 T284 1
others[7] 32 1 T218 1 T247 1 T248 2
false 11051 1 T1 21 T2 3 T3 2
true 18282 1 T1 34 T2 5 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 52 1 T62 2 T128 2 T177 2
others[1] 34 1 T177 2 T70 2 T387 2
others[2] 26 1 T96 2 T380 2 T160 2
others[3] 36 1 T96 2 T90 2 T391 2
others[4] 50 1 T96 2 T111 4 T254 2
others[5] 26 1 T70 2 T248 2 T348 4
others[6] 42 1 T177 2 T70 2 T181 2
others[7] 54 1 T13 2 T121 2 T212 2
false 9561 1 T1 20 T2 3 T3 2
true 16268 1 T1 34 T2 5 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T52 2 T100 2 T263 2
others[1] 86 1 T96 2 T70 2 T181 4
others[2] 96 1 T31 2 T98 2 T165 2
others[3] 88 1 T13 2 T31 2 T121 2
others[4] 76 1 T101 2 T212 2 T70 4
others[5] 92 1 T96 4 T91 2 T110 2
others[6] 86 1 T62 2 T99 2 T100 2
others[7] 102 1 T13 2 T62 2 T96 4
false 6790 1 T1 18 T2 2 T3 2
true 16061 1 T1 34 T2 5 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 112 1 T101 2 T128 2 T178 2
others[1] 82 1 T99 2 T100 2 T248 6
others[2] 94 1 T12 2 T31 2 T62 4
others[3] 78 1 T4 2 T96 2 T177 2
others[4] 76 1 T31 2 T97 2 T101 2
others[5] 84 1 T5 2 T111 2 T70 2
others[6] 86 1 T91 2 T70 2 T181 6
others[7] 102 1 T5 2 T13 2 T62 4
false 6790 1 T1 18 T2 2 T3 2
true 16061 1 T1 34 T2 5 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T181 2 T387 2 T67 2
others[1] 82 1 T96 2 T100 2 T110 2
others[2] 98 1 T13 2 T90 2 T111 2
others[3] 94 1 T5 2 T95 2 T177 2
others[4] 76 1 T5 2 T31 2 T181 2
others[5] 90 1 T96 2 T97 2 T128 2
others[6] 72 1 T5 2 T96 2 T177 2
others[7] 108 1 T52 2 T96 4 T128 2
false 6154 1 T1 14 T2 1 T3 2
true 16054 1 T1 34 T2 5 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 80 1 T5 2 T70 2 T181 2
others[1] 70 1 T96 2 T97 2 T101 2
others[2] 78 1 T62 2 T128 2 T110 2
others[3] 102 1 T110 2 T212 2 T70 4
others[4] 84 1 T96 4 T97 2 T181 4
others[5] 74 1 T13 2 T96 2 T99 2
others[6] 80 1 T31 2 T55 2 T91 2
others[7] 136 1 T13 2 T96 4 T91 2
false 6154 1 T1 14 T2 1 T3 2
true 16054 1 T1 34 T2 5 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 50 1 T13 2 T31 2 T75 2
others[1] 64 1 T96 4 T111 2 T177 2
others[2] 58 1 T62 2 T100 2 T177 2
others[3] 76 1 T62 2 T248 4 T288 2
others[4] 60 1 T96 2 T99 2 T212 2
others[5] 64 1 T5 2 T31 2 T100 2
others[6] 70 1 T31 2 T96 2 T181 4
others[7] 68 1 T100 2 T177 2 T389 2
false 6663 1 T1 13 T2 2 T3 2
true 17382 1 T1 35 T2 7 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 54 1 T5 2 T96 2 T100 4
others[1] 64 1 T5 2 T91 2 T70 2
others[2] 66 1 T5 2 T177 2 T178 2
others[3] 38 1 T97 2 T111 2 T123 2
others[4] 52 1 T5 2 T96 2 T97 2
others[5] 64 1 T13 2 T52 2 T31 2
others[6] 60 1 T13 2 T99 2 T111 2
others[7] 80 1 T31 2 T62 2 T177 4
false 6663 1 T1 13 T2 2 T3 2
true 17382 1 T1 35 T2 7 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 32 1 T8 1 T14 1 T30 1
others[1] 44 1 T69 2 T75 2 T212 2
others[2] 33 1 T7 1 T30 1 T219 1
others[3] 22 1 T131 1 T70 2 T218 1
others[4] 37 1 T7 1 T131 2 T70 2
others[5] 24 1 T14 1 T218 1 T271 1
others[6] 28 1 T242 2 T14 1 T285 1
others[7] 39 1 T97 2 T122 1 T218 2
false 11279 1 T1 21 T2 4 T3 2
true 18465 1 T1 34 T2 6 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 76 1 T52 2 T96 2 T111 2
others[1] 106 1 T62 2 T100 2 T110 2
others[2] 90 1 T212 2 T70 4 T380 2
others[3] 102 1 T62 2 T111 2 T112 2
others[4] 74 1 T97 2 T389 2 T181 2
others[5] 104 1 T5 2 T70 4 T389 2
others[6] 112 1 T96 2 T97 4 T100 2
others[7] 106 1 T62 2 T96 2 T91 2
false 7530 1 T1 20 T2 4 T3 2
true 16249 1 T1 34 T2 6 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 30 1 T242 2 T7 1 T122 1
others[1] 24 1 T30 1 T131 1 T287 1
others[2] 27 1 T7 1 T99 2 T165 2
others[3] 34 1 T177 2 T131 3 T263 2
others[4] 26 1 T30 1 T122 1 T218 2
others[5] 21 1 T30 2 T382 2 T218 3
others[6] 26 1 T96 2 T30 1 T271 1
others[7] 39 1 T101 2 T30 1 T131 1
false 13822 1 T1 25 T2 5 T3 3
true 2129 1 T1 1 T11 1 T5 7

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%