Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	44809	1			T1	62		T2	25		T3	39
access_err	57997	1			T1	1		T2	1		T4	9
write_blank_err	324	1			T6	1		T96	3		T7	4
ecc_uncorr_err	60423	1			T1	198		T143	347		T145	251
ecc_corr_err	1164	1			T1	3		T143	4		T52	73
no_err	83047	1			T1	20		T2	1		T3	5

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	551	1			T6	6		T7	2		T15	4
secret2	20440	1			T1	35		T2	1		T4	1
secret1	25154	1			T1	60		T3	39		T4	6
secret0	31087	1			T1	1		T4	5		T11	6
hw_cfg1	35038	1			T1	22		T3	2		T4	1
hw_cfg0	23813	1			T1	27		T2	1		T4	1
rot_creator_auth_state	20988	1			T1	31		T4	7		T11	5
rot_creator_auth_codesign	19542	1			T1	34		T4	6		T11	4
owner_sw_cfg	19861	1			T1	3		T4	2		T11	6
creator_sw_cfg	21894	1			T1	31		T3	2		T11	4
vendor_test	29396	1			T1	40		T2	25		T3	1

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3121	1			T343	182		T344	118		T345	407
fsm_err	secret1	5008	1			T3	39		T103	11		T109	66
fsm_err	secret0	3132	1			T175	30		T346	318		T181	268
fsm_err	hw_cfg1	1680	1			T239	2		T177	66		T281	46
fsm_err	hw_cfg0	4952	1			T70	39		T226	405		T181	2
fsm_err	rot_creator_auth_state	2780	1			T347	503		T348	39		T349	472
fsm_err	rot_creator_auth_codesign	2365	1			T252	396		T350	51		T185	20
fsm_err	owner_sw_cfg	3558	1			T62	36		T179	425		T177	84
fsm_err	creator_sw_cfg	4776	1			T1	30		T146	68		T93	57
fsm_err	vendor_test	13437	1			T1	32		T2	25		T11	79
access_err	life_cycle	551	1			T6	6		T7	2		T15	4
access_err	secret2	9925	1			T2	1		T4	1		T11	3
access_err	secret1	6094	1			T4	4		T12	3		T5	45
access_err	secret0	4634	1			T4	4		T12	1		T5	48
access_err	hw_cfg1	1192	1			T11	5		T12	1		T5	4
access_err	hw_cfg0	2248	1			T5	18		T13	3		T52	3
access_err	rot_creator_auth_state	5586	1			T11	3		T5	21		T13	2
access_err	rot_creator_auth_codesign	7485	1			T11	2		T12	4		T5	21
access_err	owner_sw_cfg	6240	1			T1	1		T11	2		T5	46
access_err	creator_sw_cfg	7136	1			T11	1		T12	1		T5	30
access_err	vendor_test	6906	1			T5	32		T52	11		T31	26
write_blank_err	secret2	6	1			T7	1		T177	1		T67	1
write_blank_err	secret1	17	1			T6	1		T96	1		T100	1
write_blank_err	secret0	36	1			T351	1		T249	1		T352	1
write_blank_err	hw_cfg1	56	1			T7	1		T243	1		T282	1
write_blank_err	hw_cfg0	11	1			T353	1		T219	2		T288	1
write_blank_err	rot_creator_auth_state	106	1			T96	2		T15	3		T70	2
write_blank_err	rot_creator_auth_codesign	36	1			T7	2		T70	1		T352	3
write_blank_err	owner_sw_cfg	27	1			T249	4		T288	1		T284	2
write_blank_err	creator_sw_cfg	10	1			T354	1		T355	1		T301	1
write_blank_err	vendor_test	19	1			T243	1		T219	1		T288	2
ecc_uncorr_err	secret2	2367	1			T1	34		T145	99		T7	382
ecc_uncorr_err	secret1	6011	1			T1	55		T6	146		T96	128
ecc_uncorr_err	secret0	15572	1			T143	57		T145	97		T146	132
ecc_uncorr_err	hw_cfg1	22146	1			T1	22		T143	179		T146	113
ecc_uncorr_err	hw_cfg0	5095	1			T1	26		T143	60		T146	147
ecc_uncorr_err	rot_creator_auth_state	4515	1			T1	27		T145	55		T165	9
ecc_uncorr_err	rot_creator_auth_codesign	1173	1			T1	34		T165	11		T356	19
ecc_uncorr_err	owner_sw_cfg	1339	1			T143	51		T171	51		T173	70
ecc_uncorr_err	creator_sw_cfg	2205	1			T173	139		T357	17		T358	196
ecc_corr_err	secret2	61	1			T52	12		T55	1		T119	2
ecc_corr_err	secret1	100	1			T52	3		T55	8		T146	4
ecc_corr_err	secret0	100	1			T1	1		T52	3		T55	4
ecc_corr_err	hw_cfg1	245	1			T143	2		T52	28		T55	1
ecc_corr_err	hw_cfg0	234	1			T143	1		T52	10		T55	6
ecc_corr_err	rot_creator_auth_state	101	1			T1	1		T52	3		T55	3
ecc_corr_err	rot_creator_auth_codesign	118	1			T52	8		T55	2		T95	1
ecc_corr_err	owner_sw_cfg	85	1			T1	1		T143	1		T52	1
ecc_corr_err	creator_sw_cfg	120	1			T52	5		T55	1		T95	2
no_err	secret2	4960	1			T1	1		T12	4		T5	3
no_err	secret1	7924	1			T1	5		T4	2		T11	7
no_err	secret0	7613	1			T4	1		T11	6		T12	2
no_err	hw_cfg1	9719	1			T3	2		T4	1		T11	2
no_err	hw_cfg0	11273	1			T1	1		T2	1		T4	1
no_err	rot_creator_auth_state	7900	1			T1	3		T4	7		T11	2
no_err	rot_creator_auth_codesign	8365	1			T4	6		T11	2		T12	8
no_err	owner_sw_cfg	8612	1			T1	1		T4	2		T11	4
no_err	creator_sw_cfg	7647	1			T1	1		T3	2		T11	3
no_err	vendor_test	9034	1			T1	8		T3	1		T4	7

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded