SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 22 | 0 | 22 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
creator_sw_cfg_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
hw_cfg0_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
hw_cfg1_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
lc_esc | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
owner_sw_cfg_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
rot_creator_auth_codesign_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
rot_creator_auth_state_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
secret0_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
secret1_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
secret2_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
vendor_test_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7440 | 1 | T1 | 26 | T2 | 6 | T3 | 4 | ||||
auto[1] | 4668 | 1 | T4 | 2 | T12 | 4 | T5 | 15 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7196 | 1 | T1 | 26 | T2 | 6 | T3 | 4 | ||||
auto[1] | 4912 | 1 | T4 | 8 | T9 | 1 | T12 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7243 | 1 | T1 | 26 | T2 | 6 | T3 | 4 | ||||
auto[1] | 4865 | 1 | T4 | 8 | T9 | 1 | T12 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 12061 | 1 | T1 | 26 | T2 | 5 | T3 | 4 | ||||
auto[1] | 47 | 1 | T2 | 1 | T11 | 1 | T12 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 9049 | 1 | T1 | 26 | T2 | 6 | T3 | 4 | ||||
auto[1] | 3059 | 1 | T4 | 2 | T5 | 15 | T145 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7452 | 1 | T1 | 26 | T2 | 6 | T3 | 4 | ||||
auto[1] | 4656 | 1 | T4 | 2 | T11 | 2 | T12 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 10179 | 1 | T1 | 24 | T2 | 6 | T3 | 4 | ||||
auto[1] | 1929 | 1 | T1 | 2 | T13 | 10 | T105 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7237 | 1 | T1 | 26 | T2 | 6 | T3 | 4 | ||||
auto[1] | 4871 | 1 | T4 | 10 | T9 | 1 | T11 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7208 | 1 | T1 | 26 | T2 | 3 | T3 | 4 | ||||
auto[1] | 4900 | 1 | T2 | 3 | T4 | 8 | T9 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 8580 | 1 | T1 | 26 | T2 | 6 | T3 | 4 | ||||
auto[1] | 3528 | 1 | T9 | 1 | T12 | 3 | T5 | 15 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7423 | 1 | T1 | 24 | T2 | 6 | T3 | 4 | ||||
auto[1] | 4685 | 1 | T1 | 2 | T4 | 2 | T5 | 15 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |