Assertions
dashboard | hierarchy | modlist | groups | tests | asserts
Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1451020
Category 01451020

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1451020
Severity 01451020

Summary for Assertions
NUMBERPERCENT
Total Number1451100.00
Uncovered543.72
Success139796.28
Failure00.00
Incomplete110.76
Without Attempts50.34

Summary for Cover Sequences
NUMBERPERCENT
Total Number20100.00
Uncovered00.00
All Matches20100.00
First Matches20100.00
Go previous page
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.core_tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 001285128500
tb.dut.core_tlul_assert_device.gen_device.aDataKnown_M 0013115208507835395600
tb.dut.core_tlul_assert_device.gen_device.addrSizeAlignedErr_A 0013115199501266193500
tb.dut.core_tlul_assert_device.gen_device.contigMask_M 001311520850539186700
tb.dut.core_tlul_assert_device.gen_device.dDataKnown_A 001311520850920954300
tb.dut.core_tlul_assert_device.gen_device.legalAOpcodeErr_A 0013115199501326946000
tb.dut.core_tlul_assert_device.gen_device.legalAParam_M 0013115208509344368400
tb.dut.core_tlul_assert_device.gen_device.legalDParam_A 00131152085010289108600
tb.dut.core_tlul_assert_device.gen_device.pendingReqPerSrc_M 0013115208509344368400
tb.dut.core_tlul_assert_device.gen_device.respMustHaveReq_A 00131152085010289108600
tb.dut.core_tlul_assert_device.gen_device.respOpcode_A 00131152085010289108600
tb.dut.core_tlul_assert_device.gen_device.respSzEqReqSz_A 00131152085010289108600
tb.dut.core_tlul_assert_device.gen_device.sizeGTEMaskErr_A 001311519950915878700
tb.dut.core_tlul_assert_device.gen_device.sizeMatchesMaskErr_A 001311519950940820700
tb.dut.core_tlul_assert_device.p_dbw.TlDbw_A 001285128500
tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 0013085958615000
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.AccessKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.DigestKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.DigestOffsetMustBeRepresentable_A 001118111800
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.EccErrorState_A 001308595861626500
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.ErrorKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.FsmStateKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.InitDoneKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.InitReadLocksPartition_A 00130859586127042794700
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.InitWriteLocksPartition_A 00130859586127042794700
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OffsetMustBeBlockAligned_A 001118111800
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OtpAddrKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OtpCmdKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OtpReqKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OtpSizeKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OtpWdataKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.ReadLockPropagation_A 00130859586150165325700
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.SizeMustBeBlockAligned_A 001118111800
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.TlulGntKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.TlulRdataKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.TlulReadOnReadLock_A 001308595861670700
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.TlulRerrorKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.TlulRvalidKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.WriteLockPropagation_A 001308595861267904700
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.DigestWriteLocksPartition_A 0013085958612809145800
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataOutKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccErrKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.RDataOutKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A 001118111800
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A 001308595861130773072200
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_state_regs.AssertConnected_A 001118111800
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_state_regs_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A 0013085958615000
tb.dut.gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A 0013085958615000
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.AccessKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.CnstyChkAckKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.DataKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.DigestKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.DigestOffsetMustBeRepresentable_A 001118111800
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ErrorKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.InitDoneKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.InitReadLocksPartition_A 00130859586127740946100
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.InitWriteLocksPartition_A 00130859586127740946100
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.IntegChkAckKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OffsetMustBeBlockAligned_A 001118111800
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpAddrKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpCmdKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpErrorState_A 001308595861800
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpReqKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpSizeKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpWdataKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ReadLockPropagation_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrmblCmdKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrmblDataKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrmblModeKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrmblMtxReqKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrmblSelKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrmblValidKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.SizeMustBeBlockAligned_A 001118111800
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.WriteLockPropagation_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A 001118111800
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A 001308595861130773072200
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_state_regs.AssertConnected_A 001118111800
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_state_regs_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 0013085958615000
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.AccessKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.DigestKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.DigestOffsetMustBeRepresentable_A 001118111800
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.EccErrorState_A 0013085958611290500
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.ErrorKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.FsmStateKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.InitDoneKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.InitReadLocksPartition_A 00130859586127060715700
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.InitWriteLocksPartition_A 00130859586127060715700
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OffsetMustBeBlockAligned_A 001118111800
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OtpAddrKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OtpCmdKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OtpErrorState_A 0013085958617700
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OtpReqKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OtpSizeKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OtpWdataKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.ReadLockPropagation_A 00130859586152595962800
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.SizeMustBeBlockAligned_A 001118111800
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.TlulGntKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.TlulRdataKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.TlulReadOnReadLock_A 001308595861685900
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.TlulRerrorKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.TlulRvalidKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.WriteLockPropagation_A 001308595861217787100
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.DigestWriteLocksPartition_A 0013085958612745836900
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataOutKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccErrKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.RDataOutKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A 001118111800
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A 001308595861130773072200
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_state_regs.AssertConnected_A 001118111800
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_state_regs_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 0013085958615000
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.AccessKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.DigestKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.DigestOffsetMustBeRepresentable_A 001118111800
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.EccErrorState_A 001308595861779600
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.ErrorKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.FsmStateKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.InitDoneKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.InitReadLocksPartition_A 00130859586127078519800
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.InitWriteLocksPartition_A 00130859586127078519800
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.OffsetMustBeBlockAligned_A 001118111800
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.OtpAddrKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.OtpCmdKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.OtpErrorState_A 0013085958615400
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.OtpReqKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.OtpSizeKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.OtpWdataKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.ReadLockPropagation_A 00130859586151299202300
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.SizeMustBeBlockAligned_A 001118111800
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.TlulGntKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.TlulRdataKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.TlulReadOnReadLock_A 001308595861719500
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.TlulRerrorKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.TlulRvalidKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.WriteLockPropagation_A 001308595861161582200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.DigestWriteLocksPartition_A 0013085958611756868900
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataOutKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccErrKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.RDataOutKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A 001118111800
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A 001308595861130773072200
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_state_regs.AssertConnected_A 001118111800
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_state_regs_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 0013085958615000
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.AccessKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.DigestKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.DigestOffsetMustBeRepresentable_A 001118111800
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.EccErrorState_A 001308595861658200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.ErrorKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.FsmStateKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.InitDoneKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.InitReadLocksPartition_A 00130859586127096225200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.InitWriteLocksPartition_A 00130859586127096225200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.OffsetMustBeBlockAligned_A 001118111800
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.OtpAddrKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.OtpCmdKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.OtpErrorState_A 0013085958614500
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.OtpReqKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.OtpSizeKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.OtpWdataKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.ReadLockPropagation_A 00130859586153708626300
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.SizeMustBeBlockAligned_A 001118111800
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.TlulGntKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.TlulRdataKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.TlulReadOnReadLock_A 001308595861713800
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.TlulRerrorKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.TlulRvalidKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.WriteLockPropagation_A 001308595861208453000
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.DigestWriteLocksPartition_A 0013085958612699476300
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataOutKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccErrKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.RDataOutKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A 001118111800
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A 001308595861130773072200
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_state_regs.AssertConnected_A 001118111800
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_state_regs_A 001308595861130773072200
tb.dut.gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A 0013085958615000
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.AccessKnown_A 001308595861130773072200
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.DigestKnown_A 001308595861130773072200
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.DigestOffsetMustBeRepresentable_A 001118111800
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.EccErrorState_A 0013085958611002300
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.ErrorKnown_A 001308595861130773072200
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.FsmStateKnown_A 001308595861130773072200
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.InitDoneKnown_A 001308595861130773072200
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.InitReadLocksPartition_A 00130859586127113848700
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.InitWriteLocksPartition_A 00130859586127113848700
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.OffsetMustBeBlockAligned_A 001118111800
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.OtpAddrKnown_A 001308595861130773072200
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.OtpCmdKnown_A 001308595861130773072200
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.OtpErrorState_A 0013085958613600
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.OtpReqKnown_A 001308595861130773072200
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.OtpSizeKnown_A 001308595861130773072200
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.OtpWdataKnown_A 001308595861130773072200
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.ReadLockPropagation_A 00130859586153231581300
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.SizeMustBeBlockAligned_A 001118111800
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.TlulGntKnown_A 001308595861130773072200
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.TlulRdataKnown_A 001308595861130773072200
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.TlulReadOnReadLock_A 001308595861659200
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.TlulRerrorKnown_A 001308595861130773072200
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.TlulRvalidKnown_A 001308595861130773072200
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.WriteLockPropagation_A 00130859586187827700
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.DigestWriteLocksPartition_A 0013085958611167153900
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A 001308595861130773072200
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataKnown_A 001308595861130773072200
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataOutKnown_A 001308595861130773072200
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccErrKnown_A 001308595861130773072200
Go next page
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%