| | | | | | |
tb.dut.u_otp_ctrl_dai.ScrmblDataKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.ScrmblModeKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.ScrmblMtxReqKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.ScrmblSelKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.ScrmblValidKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.gen_part_sel[0].PartEndMax_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.gen_part_sel[10].PartEndMax_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.gen_part_sel[1].PartEndMax_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.gen_part_sel[2].PartEndMax_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.gen_part_sel[3].PartEndMax_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.gen_part_sel[4].PartEndMax_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.gen_part_sel[5].PartEndMax_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.gen_part_sel[6].PartEndMax_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.gen_part_sel[7].PartEndMax_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.gen_part_sel[8].PartEndMax_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.gen_part_sel[9].PartEndMax_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.CheckHotOne_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.CheckNGreaterZero_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.GrantKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.IdxKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.Priority_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.ReqImpliesValid_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.ValidKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.u_state_regs.AssertConnected_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_dai.u_state_regs_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.EdnReqKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.EntropyWidthDividesDigestBlockWidth_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.FlashOtpKeyRspKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.FsmErrKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.KeyNonceSize0_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.KeyNonceSize1_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.KeyNonceSize2_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.KeyNonceSize3_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.KeyNonceSize4_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.KeyNonceSize5_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.KeyNonceSize6_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.NonceWidth_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.OtbnOtpKeyRspKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.ScrmblCmdKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.ScrmblDataKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.ScrmblModeKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.ScrmblMtxReqKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.ScrmblSelKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.ScrmblValidKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.SramOtpKeyRspKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.u_req_arb.CheckHotOne_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.u_req_arb.CheckNGreaterZero_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.u_req_arb.GntImpliesReady_A
| 0 | 0 | 1308595861 | 36515 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.u_req_arb.GntImpliesValid_A
| 0 | 0 | 1308595861 | 36515 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.u_req_arb.GrantKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.u_req_arb.IdxKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.u_req_arb.IndexIsCorrect_A
| 0 | 0 | 1308595861 | 36515 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.u_req_arb.LockArbDecision_A
| 0 | 0 | 1308595861 | 142297025 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.u_req_arb.NoReadyValidNoGrant_A
| 0 | 0 | 1308595861 | 1165394739 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReadyAndValidImplyGrant_A
| 0 | 0 | 1308595861 | 36515 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqAndReadyImplyGrant_A
| 0 | 0 | 1308595861 | 36515 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqImpliesValid_A
| 0 | 0 | 1308595861 | 142335983 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqStaysHighUntilGranted0_M
| 0 | 0 | 1308595861 | 142297025 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.u_req_arb.ValidKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.u_req_arb.gen_data_port_assertion.DataFlow_A
| 0 | 0 | 1308595861 | 36515 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.u_state_regs.AssertConnected_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_kdi.u_state_regs_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lci.ErrorKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lci.LcAckKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lci.LcErrKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lci.LcValueMustBeWiderThanNativeOtpWidth_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lci.LciIdleKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lci.OtpAddrKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lci.OtpCmdKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lci.OtpReqKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lci.OtpSizeKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lci.OtpWdataKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lci.u_state_regs.AssertConnected_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lci.u_state_regs_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lfsr_timer.ChkPendingKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lfsr_timer.ChkTimeoutKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lfsr_timer.CnstyChkReqKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lfsr_timer.EdnIsWideEnough_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lfsr_timer.EdnReqKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lfsr_timer.IntegChkReqKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.AssertConnected_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs.AssertConnected_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_scrmbl.CheckNumDecKeys_A
| 0 | 0 | 1308595861 | 242250 | 0 | 0 |
|
tb.dut.u_otp_ctrl_scrmbl.CheckNumDigest1_A
| 0 | 0 | 1308595861 | 133170 | 0 | 0 |
|
tb.dut.u_otp_ctrl_scrmbl.CheckNumEncKeys_A
| 0 | 0 | 1308595861 | 257731 | 0 | 0 |
|
tb.dut.u_otp_ctrl_scrmbl.DecKeyLutKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_scrmbl.DigestConstLutKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_scrmbl.DigestIvLutKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_scrmbl.EncKeyLutKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_ctrl_scrmbl.NumMaxPresentRounds_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumPhysRounds0_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumPhysRounds1_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumRounds_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedWidths_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumPhysRounds0_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumPhysRounds1_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumRounds_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedWidths_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_scrmbl.u_state_regs.AssertConnected_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_otp_ctrl_scrmbl.u_state_regs_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_rsp_fifo.DataKnown_A
| 0 | 0 | 1308595861 | 15720944 | 0 | 0 |
|
tb.dut.u_otp_rsp_fifo.DepthKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_rsp_fifo.RvalidKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_rsp_fifo.WreadyKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_otp_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 1308595861 | 15720944 | 0 | 0 |
|
tb.dut.u_part_sel_idx.CheckHotOne_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_part_sel_idx.CheckNGreaterZero_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_part_sel_idx.GrantKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_part_sel_idx.IdxKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_part_sel_idx.Priority_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_part_sel_idx.ReqImpliesValid_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_part_sel_idx.ValidKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_prim_edn_req.DataOutputDiffFromPrev_A
| 0 | 0 | 1308595861 | 614574370 | 0 | 0 |
|
tb.dut.u_prim_edn_req.DataOutputValid_A
| 0 | 0 | 1308595861 | 232290 | 0 | 0 |
|
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
| 0 | 0 | 1308595861 | 465100 | 0 | 0 |
|
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
| 0 | 0 | 1308595861 | 465002 | 0 | 0 |
|
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq
| 0 | 0 | 2091088935 | 465334 | 0 | 0 |
|
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq
| 0 | 0 | 1308595861 | 231981 | 0 | 0 |
|
tb.dut.u_prim_lc_sync_check_byp_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_prim_lc_sync_check_byp_en.OutputsKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A
| 0 | 0 | 1308595861 | 1307691071 | 0 | 3354 |
|
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.OutputsKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A
| 0 | 0 | 1308595861 | 1307691071 | 0 | 3354 |
|
tb.dut.u_prim_lc_sync_dft_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_prim_lc_sync_dft_en.OutputsKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A
| 0 | 0 | 1308595861 | 1307691071 | 0 | 3354 |
|
tb.dut.u_prim_lc_sync_escalate_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_prim_lc_sync_escalate_en.OutputsKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A
| 0 | 0 | 1308595861 | 1307691071 | 0 | 3354 |
|
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.OutputsKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.OutputDelay_A
| 0 | 0 | 1308595861 | 1307691071 | 0 | 3354 |
|
tb.dut.u_prim_lc_sync_seed_hw_rd_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_prim_lc_sync_seed_hw_rd_en.OutputsKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A
| 0 | 0 | 1308595861 | 1307691071 | 0 | 3354 |
|
tb.dut.u_reg_core.en2addrHit
| 0 | 0 | 1311519950 | 8931009 | 0 | 0 |
|
tb.dut.u_reg_core.reAfterRv
| 0 | 0 | 1311519950 | 8931008 | 0 | 0 |
|
tb.dut.u_reg_core.rePulse
| 0 | 0 | 1311519950 | 6454156 | 0 | 0 |
|
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck
| 0 | 0 | 1285 | 1285 | 0 | 0 |
|
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A
| 0 | 0 | 1285 | 1285 | 0 | 0 |
|
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert
| 0 | 0 | 1285 | 1285 | 0 | 0 |
|
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 1285 | 1285 | 0 | 0 |
|
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 1285 | 1285 | 0 | 0 |
|
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1285 | 1285 | 0 | 0 |
|
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 1285 | 1285 | 0 | 0 |
|
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1285 | 1285 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.NotOverflowed_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A
| 0 | 0 | 1311519950 | 93443684 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1285 | 1285 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A
| 0 | 0 | 1311519950 | 102891086 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1285 | 1285 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 1311519950 | 33322548 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1285 | 1285 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 1311519950 | 44735977 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1285 | 1285 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 1311519950 | 41093439 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1285 | 1285 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 1311519950 | 58155109 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 1311519950 | 1310603217 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1285 | 1285 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.maxN
| 0 | 0 | 1285 | 1285 | 0 | 0 |
|
tb.dut.u_reg_core.wePulse
| 0 | 0 | 1311519950 | 2476852 | 0 | 0 |
|
tb.dut.u_scrmbl_mtx.CheckHotOne_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_scrmbl_mtx.CheckNGreaterZero_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_scrmbl_mtx.GrantKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_scrmbl_mtx.IdxKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_scrmbl_mtx.NoReadyValidNoGrant_A
| 0 | 0 | 1308595861 | 1268464703 | 0 | 0 |
|
tb.dut.u_scrmbl_mtx.ReqImpliesValid_A
| 0 | 0 | 1308595861 | 39266019 | 0 | 0 |
|
tb.dut.u_scrmbl_mtx.ValidKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.AddrOutKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.DataIntgOptions_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.ReqOutKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.SramDwHasByteGranularity_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.SramDwIsMultipleOfTlulWidth_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.TlOutKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.TlOutPayloadKnown_A
| 0 | 0 | 1308595861 | 44705740 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.TlOutPayloadKnown_AKnownEnable
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.WdataOutKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.WeOutKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.WmaskOutKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.adapterNoReadOrWrite
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.rvalidHighReqFifoEmpty
| 0 | 0 | 1308595861 | 87867 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.rvalidHighWhenRspFifoFull
| 0 | 0 | 1308595861 | 87867 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.u_err.dataWidthOnly32_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.u_reqfifo.DataKnown_A
| 0 | 0 | 1308595861 | 45188354 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.u_reqfifo.DepthKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.u_reqfifo.RvalidKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.u_reqfifo.WreadyKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 1308595861 | 45188354 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.u_rsp_gen.DataWidthCheck_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.u_rsp_gen.PayLoadWidthCheck
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.u_rspfifo.DataKnown_A
| 0 | 0 | 1308595861 | 226569 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.u_rspfifo.DepthKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.u_rspfifo.RvalidKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.u_rspfifo.WreadyKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 1308595861 | 226569 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DataKnown_A
| 0 | 0 | 1308595861 | 570481 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DepthKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.RvalidKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.WreadyKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 1308595861 | 570481 | 0 | 0 |
|
tb.dut.u_tlul_lc_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_tlul_lc_gate.u_err_en_sync.OutputsKnown_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_lc_gate.u_state_regs.AssertConnected_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_tlul_lc_gate.u_state_regs_A
| 0 | 0 | 1308595861 | 1307730722 | 0 | 0 |
|
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1118 | 1118 | 0 | 0 |
|