Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	46494	1			T12	112		T6	92		T7	62
access_err	57014	1			T6	886		T7	3		T8	10
write_blank_err	320	1			T6	1		T8	1		T9	1
ecc_uncorr_err	59475	1			T6	403		T7	287		T8	175
ecc_corr_err	1257	1			T7	9		T90	30		T60	37
no_err	80734	1			T5	147		T12	1		T6	1090

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	523	1			T6	4		T8	2		T9	7
secret2	23646	1			T5	16		T6	205		T7	6
secret1	24785	1			T5	15		T12	1		T6	224
secret0	30695	1			T5	16		T12	112		T6	592
hw_cfg1	32685	1			T5	14		T6	181		T7	129
hw_cfg0	24221	1			T5	16		T6	181		T7	4
rot_creator_auth_state	20721	1			T5	29		T6	160		T7	48
rot_creator_auth_codesign	20007	1			T5	10		T6	196		T7	33
owner_sw_cfg	19544	1			T5	11		T6	184		T7	34
creator_sw_cfg	19313	1			T5	15		T6	304		T7	45
vendor_test	29154	1			T5	5		T6	241		T7	13

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3750	1			T192	152		T318	274		T306	6
fsm_err	secret1	2980	1			T151	4		T14	261		T214	118
fsm_err	secret0	4148	1			T12	112		T189	34		T34	160
fsm_err	hw_cfg1	2839	1			T87	42		T150	62		T15	58
fsm_err	hw_cfg0	5108	1			T184	369		T117	174		T137	11
fsm_err	rot_creator_auth_state	3672	1			T188	74		T162	16		T117	886
fsm_err	rot_creator_auth_codesign	3872	1			T7	32		T34	374		T155	136
fsm_err	owner_sw_cfg	3286	1			T7	30		T150	66		T179	10
fsm_err	creator_sw_cfg	3627	1			T6	92		T88	15		T154	5
fsm_err	vendor_test	13212	1			T90	37		T60	224		T92	116
access_err	life_cycle	523	1			T6	4		T8	2		T9	7
access_err	secret2	9904	1			T6	135		T7	3		T21	6
access_err	secret1	6076	1			T6	129		T21	9		T22	1
access_err	secret0	4817	1			T6	77		T90	2		T34	96
access_err	hw_cfg1	1246	1			T6	11		T90	3		T34	17
access_err	hw_cfg0	2331	1			T6	32		T21	1		T90	4
access_err	rot_creator_auth_state	5282	1			T6	62		T8	4		T90	10
access_err	rot_creator_auth_codesign	7185	1			T6	104		T21	2		T90	7
access_err	owner_sw_cfg	6170	1			T6	85		T8	3		T34	129
access_err	creator_sw_cfg	6862	1			T6	123		T21	2		T90	14
access_err	vendor_test	6618	1			T6	124		T8	1		T90	2
write_blank_err	secret2	14	1			T319	1		T320	1		T321	1
write_blank_err	secret1	20	1			T15	1		T111	1		T166	1
write_blank_err	secret0	35	1			T6	1		T8	1		T9	1
write_blank_err	hw_cfg1	60	1			T322	1		T117	1		T126	1
write_blank_err	hw_cfg0	12	1			T195	1		T117	1		T203	1
write_blank_err	rot_creator_auth_state	122	1			T195	9		T117	5		T215	1
write_blank_err	rot_creator_auth_codesign	27	1			T319	2		T323	2		T324	3
write_blank_err	owner_sw_cfg	11	1			T324	6		T311	1		T312	1
write_blank_err	creator_sw_cfg	5	1			T325	1		T227	1		T326	1
write_blank_err	vendor_test	14	1			T117	2		T327	1		T227	1
ecc_uncorr_err	secret2	5287	1			T155	69		T151	28		T328	94
ecc_uncorr_err	secret1	8218	1			T153	40		T155	229		T15	574
ecc_uncorr_err	secret0	14467	1			T6	403		T7	75		T8	175
ecc_uncorr_err	hw_cfg1	18906	1			T7	126		T151	27		T322	708
ecc_uncorr_err	hw_cfg0	5600	1			T155	131		T151	17		T152	196
ecc_uncorr_err	rot_creator_auth_state	3695	1			T7	45		T154	4		T151	10
ecc_uncorr_err	rot_creator_auth_codesign	696	1			T150	126		T329	3		T330	32
ecc_uncorr_err	owner_sw_cfg	1621	1			T150	68		T155	135		T152	153
ecc_uncorr_err	creator_sw_cfg	985	1			T7	41		T150	68		T151	15
ecc_corr_err	secret2	64	1			T7	2		T60	1		T57	4
ecc_corr_err	secret1	106	1			T7	2		T90	3		T60	9
ecc_corr_err	secret0	134	1			T90	5		T57	8		T155	2
ecc_corr_err	hw_cfg1	221	1			T7	2		T90	7		T60	5
ecc_corr_err	hw_cfg0	208	1			T7	2		T90	9		T60	6
ecc_corr_err	rot_creator_auth_state	122	1			T90	2		T60	1		T155	4
ecc_corr_err	rot_creator_auth_codesign	99	1			T90	2		T60	1		T57	7
ecc_corr_err	owner_sw_cfg	130	1			T90	1		T60	4		T57	7
ecc_corr_err	creator_sw_cfg	173	1			T7	1		T90	1		T60	10
no_err	secret2	4627	1			T5	16		T6	70		T7	1
no_err	secret1	7385	1			T5	15		T12	1		T6	95
no_err	secret0	7094	1			T5	16		T6	111		T7	1
no_err	hw_cfg1	9413	1			T5	14		T6	170		T7	1
no_err	hw_cfg0	10962	1			T5	16		T6	149		T7	2
no_err	rot_creator_auth_state	7828	1			T5	29		T6	98		T7	3
no_err	rot_creator_auth_codesign	8128	1			T5	10		T6	92		T7	1
no_err	owner_sw_cfg	8326	1			T5	11		T6	99		T7	4
no_err	creator_sw_cfg	7661	1			T5	15		T6	89		T7	3
no_err	vendor_test	9310	1			T5	5		T6	117		T7	13

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded