Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

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Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
secret1_lock	2	0	2	100.00	100	1	1	2
sram_index	4	0	4	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sram_req_lock_cross	8	0	8	100.00	100	1	1	0

Summary for Variable secret1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret1_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1263

1

T7

12

T34

1

T154

14

auto[1]

1173

1

T34

6

T80

26

T86

7

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Summary for Variable sram_index

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for sram_index

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_key[0x0]	152	1			T34	1		T86	5		T192	7
sram_key[0x1]	746	1			T7	2		T80	10		T154	5
sram_key[0x2]	768	1			T7	5		T34	1		T80	9
sram_key[0x3]	770	1			T7	5		T34	5		T80	7

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Summary for Cross sram_req_lock_cross

Samples crossed: sram_index secret1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for sram_req_lock_cross

Bins

sram_index	secret1_lock	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_key[0x0]	auto[0]	95	1			T86	4		T192	4		T366	3
sram_key[0x0]	auto[1]	57	1			T34	1		T86	1		T192	3
sram_key[0x1]	auto[0]	390	1			T7	2		T154	5		T9	1
sram_key[0x1]	auto[1]	356	1			T80	10		T86	2		T117	20
sram_key[0x2]	auto[0]	407	1			T7	5		T34	1		T154	5
sram_key[0x2]	auto[1]	361	1			T80	9		T86	2		T117	20
sram_key[0x3]	auto[0]	371	1			T7	5		T154	4		T9	1
sram_key[0x3]	auto[1]	399	1			T34	5		T80	7		T86	2