Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	55515	1			T4	372		T10	48		T21	353
access_err	64488	1			T1	18		T4	262		T5	234
write_blank_err	450	1			T1	2		T7	1		T13	1
ecc_uncorr_err	70386	1			T1	398		T7	377		T13	234
ecc_corr_err	1383	1			T1	1		T34	1		T35	6
no_err	96560	1			T1	21		T3	7		T4	510

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	684	1			T1	7		T7	2		T13	9
secret2	22636	1			T1	6		T3	1		T4	176
secret1	26665	1			T1	401		T4	71		T5	33
secret0	40265	1			T1	3		T4	67		T5	33
hw_cfg1	35437	1			T1	9		T3	2		T4	79
hw_cfg0	32398	1			T3	4		T4	344		T5	20
rot_creator_auth_state	26469	1			T4	78		T5	46		T7	9
rot_creator_auth_codesign	24058	1			T1	9		T4	74		T5	58
owner_sw_cfg	22075	1			T4	92		T5	26		T7	47
creator_sw_cfg	22998	1			T1	5		T4	85		T5	52
vendor_test	35097	1			T4	78		T5	31		T7	12

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	1880	1			T4	88		T10	48		T193	25
fsm_err	secret1	3196	1			T11	140		T169	129		T18	1
fsm_err	secret0	4561	1			T246	109		T68	99		T190	1
fsm_err	hw_cfg1	2960	1			T247	27		T342	286		T258	128
fsm_err	hw_cfg0	8938	1			T4	284		T102	534		T34	53
fsm_err	rot_creator_auth_state	4764	1			T21	353		T100	1		T34	282
fsm_err	rot_creator_auth_codesign	4613	1			T18	26		T343	17		T240	12
fsm_err	owner_sw_cfg	3810	1			T159	49		T344	182		T345	377
fsm_err	creator_sw_cfg	4098	1			T126	43		T139	19		T250	226
fsm_err	vendor_test	16695	1			T35	26		T42	55		T53	135
access_err	life_cycle	684	1			T1	7		T7	2		T13	9
access_err	secret2	11329	1			T1	6		T4	68		T5	35
access_err	secret1	6047	1			T5	25		T20	19		T34	82
access_err	secret0	4543	1			T4	2		T5	27		T19	3
access_err	hw_cfg1	1328	1			T1	1		T4	8		T10	2
access_err	hw_cfg0	2120	1			T5	5		T19	3		T34	28
access_err	rot_creator_auth_state	6134	1			T4	42		T5	23		T7	2
access_err	rot_creator_auth_codesign	8205	1			T1	1		T4	37		T5	52
access_err	owner_sw_cfg	7561	1			T4	40		T5	8		T7	12
access_err	creator_sw_cfg	8514	1			T1	3		T4	37		T5	36
access_err	vendor_test	8023	1			T4	28		T5	23		T7	1
write_blank_err	secret2	10	1			T94	1		T178	1		T189	1
write_blank_err	secret1	19	1			T1	1		T227	1		T18	1
write_blank_err	secret0	57	1			T13	1		T92	1		T189	1
write_blank_err	hw_cfg1	67	1			T1	1		T7	1		T34	3
write_blank_err	hw_cfg0	31	1			T65	1		T71	1		T18	1
write_blank_err	rot_creator_auth_state	152	1			T34	10		T94	1		T65	1
write_blank_err	rot_creator_auth_codesign	41	1			T34	2		T94	3		T338	5
write_blank_err	owner_sw_cfg	28	1			T94	1		T117	5		T346	3
write_blank_err	creator_sw_cfg	16	1			T347	1		T348	5		T235	2
write_blank_err	vendor_test	29	1			T34	2		T65	1		T18	1
ecc_uncorr_err	secret2	3698	1			T94	531		T178	213		T189	602
ecc_uncorr_err	secret1	7497	1			T1	398		T227	454		T18	258
ecc_uncorr_err	secret0	21642	1			T13	234		T126	48		T92	449
ecc_uncorr_err	hw_cfg1	19316	1			T7	377		T34	431		T126	103
ecc_uncorr_err	hw_cfg0	8299	1			T65	443		T71	503		T18	434
ecc_uncorr_err	rot_creator_auth_state	6335	1			T126	52		T138	26		T250	674
ecc_uncorr_err	rot_creator_auth_codesign	1580	1			T126	86		T139	25		T183	54
ecc_uncorr_err	owner_sw_cfg	808	1			T139	23		T349	46		T183	111
ecc_uncorr_err	creator_sw_cfg	1211	1			T349	51		T159	40		T350	7
ecc_corr_err	secret2	109	1			T35	3		T53	9		T47	8
ecc_corr_err	secret1	117	1			T126	2		T42	2		T52	4
ecc_corr_err	secret0	165	1			T126	3		T42	1		T52	3
ecc_corr_err	hw_cfg1	278	1			T1	1		T34	1		T35	1
ecc_corr_err	hw_cfg0	242	1			T126	2		T42	1		T92	1
ecc_corr_err	rot_creator_auth_state	117	1			T35	2		T126	3		T42	4
ecc_corr_err	rot_creator_auth_codesign	124	1			T53	2		T138	1		T139	2
ecc_corr_err	owner_sw_cfg	118	1			T126	2		T42	3		T53	11
ecc_corr_err	creator_sw_cfg	113	1			T126	1		T53	9		T138	6
no_err	secret2	5610	1			T3	1		T4	20		T5	1
no_err	secret1	9789	1			T1	2		T4	71		T5	8
no_err	secret0	9297	1			T1	3		T4	65		T5	6
no_err	hw_cfg1	11488	1			T1	6		T3	2		T4	71
no_err	hw_cfg0	12768	1			T3	4		T4	60		T5	15
no_err	rot_creator_auth_state	8967	1			T4	36		T5	23		T7	7
no_err	rot_creator_auth_codesign	9495	1			T1	8		T4	37		T5	6
no_err	owner_sw_cfg	9750	1			T4	52		T5	18		T7	35
no_err	creator_sw_cfg	9046	1			T1	2		T4	48		T5	16
no_err	vendor_test	10350	1			T4	50		T5	8		T7	11

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded