Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	2	0	2	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

822

1

T4

15

T11

7

T65

14

all_values[1]

822

1

T4

15

T11

7

T65

14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

908

1

T4

17

T11

8

T65

13

auto[1]

736

1

T4

13

T11

6

T65

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

619

1

T4

14

T11

5

T65

7

auto[1]

1025

1

T4

16

T11

9

T65

21

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

956

1

T4

16

T11

8

T65

12

auto[1]

688

1

T4

14

T11

6

T65

16

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	12	0	12	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

194

1

T4

1

T65

2

T227

5

all_values[0]

auto[0]

auto[0]

auto[1]

82

1

T11

1

T129

2

T348

2

all_values[0]

auto[0]

auto[1]

auto[0]

117

1

T4

4

T65

3

T209

1

all_values[0]

auto[0]

auto[1]

auto[1]

85

1

T4

1

T11

2

T65

1

all_values[0]

auto[1]

auto[0]

auto[1]

185

1

T4

6

T11

2

T65

5

all_values[0]

auto[1]

auto[1]

auto[1]

159

1

T4

3

T11

2

T65

3

all_values[1]

auto[0]

auto[0]

auto[0]

171

1

T4

7

T11

3

T65

1

all_values[1]

auto[0]

auto[0]

auto[1]

84

1

T4

1

T227

1

T178

1

all_values[1]

auto[0]

auto[1]

auto[0]

137

1

T4

2

T11

2

T65

1

all_values[1]

auto[0]

auto[1]

auto[1]

86

1

T65

4

T178

1

T277

1

all_values[1]

auto[1]

auto[0]

auto[1]

192

1

T4

2

T11

2

T65

5

all_values[1]

auto[1]

auto[1]

auto[1]

152

1

T4

3

T65

3

T250

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal