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Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 14624 1 T1 4 T2 3 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 14624 1 T1 4 T2 3 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 10418 1 T1 2 T2 2 T3 9
true 17010 1 T1 5 T2 4 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 11351 1 T1 2 T2 2 T3 10
true 17057 1 T1 5 T2 4 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 68 1 T175 2 T358 4 T323 2
others[1] 118 1 T32 4 T92 4 T110 2
others[2] 74 1 T110 2 T212 2 T359 2
others[3] 110 1 T3 2 T4 2 T32 2
others[4] 92 1 T4 2 T82 2 T110 2
others[5] 134 1 T4 2 T91 2 T92 2
others[6] 98 1 T92 2 T177 2 T360 2
others[7] 130 1 T4 2 T32 2 T90 2
false 14624 1 T1 4 T2 3 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 108 1 T4 2 T90 2 T92 2
others[1] 116 1 T4 2 T91 4 T110 2
others[2] 82 1 T92 2 T176 2 T181 2
others[3] 92 1 T92 2 T110 4 T114 2
others[4] 86 1 T92 2 T93 2 T82 2
others[5] 104 1 T32 2 T91 2 T92 2
others[6] 122 1 T4 4 T23 2 T90 2
others[7] 94 1 T4 2 T23 2 T90 2
false 14624 1 T1 4 T2 3 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 124 1 T4 2 T92 6 T239 2
others[1] 110 1 T91 2 T93 2 T94 2
others[2] 108 1 T32 4 T361 2 T181 2
others[3] 88 1 T89 2 T91 2 T81 2
others[4] 62 1 T4 2 T90 2 T91 2
others[5] 72 1 T81 2 T173 2 T178 2
others[6] 110 1 T32 2 T82 2 T94 2
others[7] 114 1 T4 2 T92 2 T81 2
false 14624 1 T1 4 T2 3 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T32 2 T84 2 T176 2
others[1] 52 1 T81 2 T361 2 T322 2
others[2] 74 1 T3 2 T32 2 T81 2
others[3] 64 1 T212 2 T362 2 T151 4
others[4] 60 1 T81 6 T176 2 T178 2
others[5] 40 1 T363 2 T212 2 T213 2
others[6] 60 1 T4 2 T90 2 T81 2
others[7] 86 1 T4 4 T90 2 T81 2
false 14624 1 T1 4 T2 3 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T91 2 T81 2 T173 2
others[1] 84 1 T92 2 T172 2 T93 2
others[2] 100 1 T32 2 T92 4 T177 2
others[3] 112 1 T91 4 T94 2 T110 2
others[4] 86 1 T4 2 T82 2 T110 2
others[5] 116 1 T81 2 T84 2 T175 2
others[6] 72 1 T92 2 T181 2 T322 2
others[7] 120 1 T4 2 T92 2 T173 2
false 14624 1 T1 4 T2 3 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 48 1 T91 2 T174 2 T177 2
others[1] 46 1 T4 2 T92 2 T94 2
others[2] 26 1 T110 2 T175 2 T151 2
others[3] 30 1 T4 2 T92 2 T364 2
others[4] 28 1 T92 4 T93 2 T177 2
others[5] 26 1 T365 2 T183 2 T366 2
others[6] 50 1 T4 2 T32 2 T92 2
others[7] 42 1 T92 4 T174 2 T177 2
false 14624 1 T1 4 T2 3 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 104 1 T81 2 T82 2 T181 4
others[1] 110 1 T32 2 T89 2 T91 2
others[2] 92 1 T4 2 T90 2 T92 4
others[3] 124 1 T4 4 T90 2 T91 4
others[4] 124 1 T32 2 T81 4 T82 2
others[5] 98 1 T3 2 T110 2 T173 2
others[6] 104 1 T93 2 T81 4 T110 2
others[7] 118 1 T32 2 T89 2 T90 2
false 14624 1 T1 4 T2 3 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 120 1 T90 2 T92 2 T81 2
others[1] 88 1 T92 4 T110 2 T267 2
others[2] 74 1 T4 2 T81 4 T174 2
others[3] 110 1 T4 8 T81 2 T110 2
others[4] 66 1 T90 2 T110 4 T239 2
others[5] 100 1 T32 2 T91 2 T81 2
others[6] 112 1 T81 2 T82 4 T110 2
others[7] 104 1 T4 2 T32 2 T91 2
false 14624 1 T1 4 T2 3 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 82 1 T4 2 T23 2 T81 2
others[1] 108 1 T4 2 T81 2 T359 2
others[2] 86 1 T4 2 T32 2 T91 2
others[3] 76 1 T3 2 T4 2 T90 4
others[4] 78 1 T81 4 T110 2 T212 2
others[5] 54 1 T32 2 T81 2 T110 2
others[6] 124 1 T4 2 T90 2 T91 2
others[7] 98 1 T92 2 T84 2 T181 2
false 14624 1 T1 4 T2 3 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 92 1 T3 2 T32 2 T91 2
others[1] 86 1 T93 2 T81 2 T94 4
others[2] 94 1 T4 4 T32 4 T81 2
others[3] 66 1 T90 2 T82 2 T110 4
others[4] 76 1 T4 2 T84 2 T173 2
others[5] 82 1 T32 2 T81 2 T367 2
others[6] 104 1 T81 2 T110 2 T173 2
others[7] 116 1 T32 2 T90 2 T92 2
false 14624 1 T1 4 T2 3 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 94 1 T4 2 T92 4 T93 2
others[1] 98 1 T4 4 T82 2 T84 2
others[2] 102 1 T90 2 T91 2 T179 2
others[3] 102 1 T82 2 T84 2 T110 2
others[4] 104 1 T4 4 T90 2 T93 2
others[5] 134 1 T4 2 T32 2 T92 4
others[6] 96 1 T4 2 T91 2 T81 2
others[7] 116 1 T92 2 T181 4 T322 2
false 14624 1 T1 4 T2 3 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 49 1 T6 2 T114 2 T146 2
others[1] 35 1 T12 3 T87 1 T302 2
others[2] 30 1 T94 2 T269 1 T302 1
others[3] 35 1 T12 1 T146 1 T269 1
others[4] 20 1 T87 1 T252 1 T232 1
others[5] 30 1 T11 1 T12 2 T146 1
others[6] 30 1 T11 1 T87 1 T144 1
others[7] 38 1 T11 1 T90 2 T87 1
false 14624 1 T1 4 T2 3 T3 14
true 2421 1 T2 1 T3 1 T4 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 37 1 T11 1 T90 2 T94 2
others[1] 26 1 T145 1 T252 1 T368 1
others[2] 34 1 T6 1 T12 1 T87 1
others[3] 36 1 T11 2 T302 2 T369 3
others[4] 36 1 T12 1 T302 3 T370 1
others[5] 28 1 T12 1 T87 1 T144 1
others[6] 36 1 T6 1 T12 1 T146 1
others[7] 35 1 T12 2 T87 2 T146 1
false 11864 1 T1 2 T2 2 T3 10
true 19418 1 T1 5 T2 4 T3 15


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 112 1 T4 2 T91 2 T82 2
others[1] 96 1 T91 2 T82 2 T173 2
others[2] 132 1 T32 4 T90 2 T92 4
others[3] 90 1 T4 2 T92 4 T110 4
others[4] 96 1 T82 2 T173 2 T179 2
others[5] 78 1 T92 2 T174 2 T181 2
others[6] 90 1 T92 2 T81 4 T371 2
others[7] 130 1 T3 2 T4 4 T32 4
false 7792 1 T1 2 T2 1 T3 5
true 17097 1 T1 5 T2 4 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 100 1 T4 2 T32 2 T90 2
others[1] 92 1 T23 2 T92 2 T361 2
others[2] 90 1 T90 2 T91 2 T92 6
others[3] 90 1 T4 6 T92 2 T181 2
others[4] 104 1 T4 2 T110 2 T175 2
others[5] 110 1 T90 2 T110 2 T176 2
others[6] 108 1 T23 2 T91 4 T82 2
others[7] 110 1 T91 2 T94 2 T110 2
false 6842 1 T1 2 T2 1 T3 1
true 16868 1 T1 5 T2 4 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 100 1 T4 2 T81 2 T94 2
others[1] 96 1 T92 2 T81 2 T174 2
others[2] 102 1 T91 2 T92 2 T94 2
others[3] 90 1 T93 2 T94 2 T173 2
others[4] 98 1 T32 2 T93 2 T81 2
others[5] 92 1 T32 2 T90 2 T91 2
others[6] 92 1 T4 4 T32 2 T178 2
others[7] 118 1 T89 2 T91 2 T92 2
false 7316 1 T1 2 T2 2 T3 2
true 16887 1 T1 5 T2 4 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 35 1 T129 2 T146 1 T269 1
others[1] 29 1 T87 2 T252 3 T269 1
others[2] 34 1 T12 1 T252 1 T308 1
others[3] 24 1 T6 1 T148 1 T314 2
others[4] 18 1 T31 1 T146 2 T328 1
others[5] 32 1 T6 1 T12 1 T145 1
others[6] 25 1 T6 1 T84 2 T252 1
others[7] 43 1 T6 1 T12 1 T87 1
false 11800 1 T1 2 T2 2 T3 10
true 19398 1 T1 5 T2 4 T3 15


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 56 1 T32 2 T81 2 T362 2
others[1] 52 1 T81 2 T179 2 T181 2
others[2] 58 1 T90 2 T84 2 T179 2
others[3] 80 1 T81 4 T178 2 T181 2
others[4] 58 1 T4 2 T32 2 T212 4
others[5] 78 1 T176 2 T361 2 T218 2
others[6] 50 1 T4 2 T81 2 T218 2
others[7] 94 1 T3 2 T4 2 T90 2
false 9103 1 T1 1 T2 1 T3 5
true 17093 1 T1 5 T2 4 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 37 1 T6 1 T87 1 T145 1
others[1] 19 1 T12 1 T146 1 T269 1
others[2] 33 1 T6 1 T144 1 T145 1
others[3] 40 1 T11 1 T87 1 T308 1
others[4] 23 1 T6 1 T11 1 T145 1
others[5] 28 1 T87 1 T269 1 T148 1
others[6] 33 1 T6 2 T87 1 T144 1
others[7] 33 1 T11 1 T146 1 T252 1
false 11740 1 T1 2 T2 2 T3 10
true 19347 1 T1 5 T2 4 T3 15


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 110 1 T92 2 T81 2 T94 2
others[1] 94 1 T91 2 T110 2 T173 2
others[2] 94 1 T91 2 T92 4 T110 2
others[3] 102 1 T239 2 T218 2 T322 2
others[4] 98 1 T4 2 T81 4 T175 2
others[5] 88 1 T4 2 T91 2 T172 2
others[6] 88 1 T92 4 T81 2 T253 2
others[7] 100 1 T32 2 T372 2 T181 2
false 7711 1 T1 2 T2 2 T3 5
true 17010 1 T1 5 T2 4 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 43 1 T4 2 T6 1 T23 2
others[1] 29 1 T87 1 T114 2 T144 2
others[2] 34 1 T6 1 T145 1 T328 2
others[3] 29 1 T6 1 T11 1 T145 1
others[4] 37 1 T6 2 T11 1 T12 1
others[5] 19 1 T6 1 T87 3 T146 1
others[6] 34 1 T6 1 T87 1 T232 1
others[7] 52 1 T12 2 T31 2 T87 1
false 11685 1 T1 2 T2 2 T3 10
true 19331 1 T1 5 T2 4 T3 16


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 42 1 T4 2 T91 2 T92 2
others[1] 34 1 T92 2 T110 2 T174 2
others[2] 32 1 T92 6 T93 2 T151 2
others[3] 28 1 T92 2 T177 2 T359 2
others[4] 36 1 T4 2 T110 2 T230 4
others[5] 36 1 T32 2 T177 2 T181 2
others[6] 52 1 T4 2 T175 2 T219 2
others[7] 36 1 T92 2 T94 2 T174 2
false 9998 1 T1 2 T2 2 T3 10
true 17075 1 T1 5 T2 4 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 122 1 T3 2 T90 4 T91 4
others[1] 104 1 T32 4 T93 2 T81 2
others[2] 106 1 T4 2 T91 2 T92 2
others[3] 92 1 T92 2 T110 2 T173 2
others[4] 96 1 T94 2 T110 4 T267 2
others[5] 92 1 T81 4 T110 4 T176 2
others[6] 134 1 T4 2 T32 2 T90 2
others[7] 128 1 T4 2 T89 4 T92 2
false 7073 1 T1 2 T2 2 T3 4
true 16873 1 T1 5 T2 4 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T4 4 T32 2 T91 2
others[1] 122 1 T4 2 T90 2 T177 2
others[2] 86 1 T4 4 T32 2 T91 2
others[3] 98 1 T90 2 T110 2 T267 2
others[4] 104 1 T4 2 T92 2 T81 2
others[5] 90 1 T81 4 T82 2 T114 2
others[6] 90 1 T92 4 T173 2 T174 2
others[7] 100 1 T81 2 T175 2 T371 2
false 7073 1 T1 2 T2 2 T3 4
true 16873 1 T1 5 T2 4 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 96 1 T4 2 T32 2 T81 4
others[1] 80 1 T23 2 T81 4 T110 2
others[2] 80 1 T32 2 T90 2 T91 2
others[3] 72 1 T4 2 T81 2 T181 2
others[4] 92 1 T3 2 T92 2 T84 2
others[5] 84 1 T90 2 T91 2 T81 2
others[6] 64 1 T4 4 T94 2 T181 2
others[7] 138 1 T4 2 T90 2 T84 2
false 6457 1 T1 2 T2 2 T3 1
true 16865 1 T1 5 T2 4 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 86 1 T84 2 T94 2 T173 2
others[1] 70 1 T32 2 T81 2 T181 2
others[2] 92 1 T4 2 T92 2 T81 2
others[3] 102 1 T4 2 T32 2 T82 2
others[4] 102 1 T4 2 T32 2 T90 2
others[5] 82 1 T3 2 T32 2 T173 2
others[6] 82 1 T32 2 T90 2 T93 2
others[7] 100 1 T91 2 T110 2 T176 2
false 6457 1 T1 2 T2 2 T3 1
true 16865 1 T1 5 T2 4 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 78 1 T4 2 T92 2 T24 2
others[1] 80 1 T81 4 T82 2 T94 2
others[2] 74 1 T81 2 T110 2 T175 2
others[3] 98 1 T92 4 T81 2 T110 2
others[4] 72 1 T81 2 T110 2 T361 2
others[5] 66 1 T32 2 T110 2 T151 2
others[6] 72 1 T92 2 T81 2 T39 2
others[7] 68 1 T92 2 T94 2 T181 2
false 6865 1 T1 2 T2 2 T3 6
true 18191 1 T1 5 T2 5 T3 16


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 88 1 T81 4 T94 2 T212 2
others[1] 54 1 T92 2 T176 2 T151 2
others[2] 78 1 T92 2 T82 4 T361 2
others[3] 76 1 T4 4 T214 2 T154 2
others[4] 68 1 T110 2 T151 2 T373 2
others[5] 50 1 T90 2 T213 2 T374 2
others[6] 78 1 T94 2 T114 2 T359 2
others[7] 106 1 T81 2 T94 2 T371 2
false 6865 1 T1 2 T2 2 T3 6
true 18191 1 T1 5 T2 5 T3 16


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 28 1 T145 1 T252 2 T370 1
others[1] 40 1 T6 1 T252 1 T308 1
others[2] 27 1 T144 1 T145 1 T269 1
others[3] 31 1 T31 1 T308 1 T306 1
others[4] 26 1 T4 2 T87 1 T144 2
others[5] 33 1 T6 1 T145 1 T252 1
others[6] 27 1 T81 2 T306 1 T212 4
others[7] 40 1 T12 1 T170 1 T110 4
false 11944 1 T1 3 T2 2 T3 10
true 19494 1 T1 5 T2 4 T3 15


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T93 2 T82 2 T110 2
others[1] 98 1 T81 2 T84 2 T181 4
others[2] 116 1 T82 2 T174 2 T177 2
others[3] 122 1 T4 6 T32 2 T92 4
others[4] 104 1 T4 6 T90 2 T91 2
others[5] 86 1 T90 2 T172 2 T177 2
others[6] 108 1 T4 2 T91 2 T92 2
others[7] 122 1 T179 2 T239 4 T181 2
false 7791 1 T1 1 T2 1 T3 10
true 17069 1 T1 5 T2 4 T3 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 28 1 T6 1 T129 2 T252 1
others[1] 32 1 T31 1 T84 2 T87 1
others[2] 27 1 T6 1 T146 2 T252 1
others[3] 33 1 T6 1 T87 1 T146 2
others[4] 18 1 T308 1 T302 1 T309 2
others[5] 22 1 T12 1 T87 1 T328 1
others[6] 45 1 T252 1 T269 1 T308 2
others[7] 35 1 T6 1 T12 2 T308 1
false 14624 1 T1 4 T2 3 T3 14
true 2442 1 T2 1 T3 1 T4 22

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%