Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	48145	1			T1	3		T2	79		T8	27
access_err	62744	1			T2	11		T4	295		T6	288
write_blank_err	461	1			T4	15		T6	7		T7	6
ecc_uncorr_err	66030	1			T4	1515		T6	1096		T7	335
ecc_corr_err	1166	1			T22	37		T23	3		T193	4
no_err	92157	1			T1	7		T2	7		T3	2

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	804	1			T4	8		T6	8		T7	6
secret2	24432	1			T1	3		T2	4		T3	2
secret1	27552	1			T1	6		T4	94		T6	61
secret0	33684	1			T2	3		T4	920		T6	80
hw_cfg1	37412	1			T4	642		T6	607		T9	5
hw_cfg0	27577	1			T2	81		T4	345		T6	67
rot_creator_auth_state	22740	1			T4	85		T6	91		T9	7
rot_creator_auth_codesign	22553	1			T2	1		T4	108		T6	118
owner_sw_cfg	20661	1			T1	1		T2	2		T4	196
creator_sw_cfg	21117	1			T8	27		T4	86		T6	114
vendor_test	32171	1			T2	6		T4	142		T6	77

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2745	1			T11	40		T129	30		T269	46
fsm_err	secret1	4145	1			T1	3		T169	167		T142	617
fsm_err	secret0	5030	1			T4	264		T320	37		T204	51
fsm_err	hw_cfg1	3477	1			T170	237		T227	328		T146	21
fsm_err	hw_cfg0	5766	1			T2	79		T4	269		T97	295
fsm_err	rot_creator_auth_state	2580	1			T130	34		T87	169		T326	25
fsm_err	rot_creator_auth_codesign	3782	1			T129	23		T110	148		T232	116
fsm_err	owner_sw_cfg	3024	1			T4	105		T327	210		T322	48
fsm_err	creator_sw_cfg	3448	1			T8	27		T110	60		T182	55
fsm_err	vendor_test	14148	1			T9	239		T10	8		T22	251
access_err	life_cycle	804	1			T4	8		T6	8		T7	6
access_err	secret2	10953	1			T2	4		T4	57		T6	76
access_err	secret1	6054	1			T4	39		T23	2		T11	4
access_err	secret0	4880	1			T2	2		T4	29		T6	2
access_err	hw_cfg1	1330	1			T4	10		T6	1		T10	3
access_err	hw_cfg0	2428	1			T4	10		T22	3		T32	14
access_err	rot_creator_auth_state	5810	1			T4	11		T6	60		T9	3
access_err	rot_creator_auth_codesign	7987	1			T4	39		T6	32		T7	1
access_err	owner_sw_cfg	7295	1			T2	1		T4	33		T6	41
access_err	creator_sw_cfg	7732	1			T4	25		T6	40		T9	6
access_err	vendor_test	7471	1			T2	4		T4	34		T6	28
write_blank_err	secret2	11	1			T4	1		T6	1		T145	1
write_blank_err	secret1	25	1			T181	1		T328	1		T148	1
write_blank_err	secret0	46	1			T4	1		T167	1		T32	1
write_blank_err	hw_cfg1	77	1			T4	1		T6	1		T7	1
write_blank_err	hw_cfg0	15	1			T193	1		T329	1		T194	1
write_blank_err	rot_creator_auth_state	155	1			T4	11		T6	5		T7	5
write_blank_err	rot_creator_auth_codesign	53	1			T167	1		T330	1		T270	2
write_blank_err	owner_sw_cfg	45	1			T11	1		T329	4		T302	2
write_blank_err	creator_sw_cfg	9	1			T193	1		T217	1		T257	1
write_blank_err	vendor_test	25	1			T4	1		T330	1		T146	1
ecc_uncorr_err	secret2	5011	1			T4	371		T6	531		T129	25
ecc_uncorr_err	secret1	8269	1			T319	9		T139	61		T159	26
ecc_uncorr_err	secret0	15249	1			T4	574		T167	341		T32	460
ecc_uncorr_err	hw_cfg1	21987	1			T4	570		T6	565		T7	335
ecc_uncorr_err	hw_cfg0	6702	1			T193	558		T129	62		T130	12
ecc_uncorr_err	rot_creator_auth_state	5260	1			T129	17		T130	9		T139	63
ecc_uncorr_err	rot_creator_auth_codesign	1512	1			T139	67		T331	125		T151	149
ecc_uncorr_err	owner_sw_cfg	991	1			T192	54		T150	54		T166	40
ecc_uncorr_err	creator_sw_cfg	1049	1			T331	69		T332	7		T333	47
ecc_corr_err	secret2	78	1			T130	3		T39	5		T166	1
ecc_corr_err	secret1	95	1			T22	1		T130	3		T139	1
ecc_corr_err	secret0	99	1			T22	3		T129	2		T130	3
ecc_corr_err	hw_cfg1	202	1			T22	1		T130	2		T81	6
ecc_corr_err	hw_cfg0	214	1			T22	7		T129	3		T130	2
ecc_corr_err	rot_creator_auth_state	119	1			T22	11		T23	1		T129	3
ecc_corr_err	rot_creator_auth_codesign	122	1			T22	7		T23	2		T129	2
ecc_corr_err	owner_sw_cfg	93	1			T22	1		T129	2		T130	2
ecc_corr_err	creator_sw_cfg	144	1			T22	6		T193	4		T129	2
no_err	secret2	5634	1			T1	3		T3	2		T4	40
no_err	secret1	8964	1			T1	3		T4	55		T6	61
no_err	secret0	8380	1			T2	1		T4	52		T6	78
no_err	hw_cfg1	10339	1			T4	61		T6	40		T9	5
no_err	hw_cfg0	12452	1			T2	2		T4	66		T6	67
no_err	rot_creator_auth_state	8816	1			T4	63		T6	26		T9	4
no_err	rot_creator_auth_codesign	9097	1			T2	1		T4	69		T6	86
no_err	owner_sw_cfg	9213	1			T1	1		T2	1		T4	58
no_err	creator_sw_cfg	8735	1			T4	61		T6	74		T9	6
no_err	vendor_test	10527	1			T2	2		T4	107		T6	49

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded