Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	53337	1			T3	272		T4	24		T5	12
access_err	61987	1			T4	113		T5	10		T6	183
write_blank_err	459	1			T7	1		T8	2		T116	1
ecc_uncorr_err	68256	1			T7	123		T138	186		T139	238
ecc_corr_err	1250	1			T5	2		T11	3		T138	6
no_err	92190	1			T3	3		T4	197		T5	10

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	767	1			T13	11		T14	5		T15	17
secret2	22126	1			T3	272		T4	32		T5	1
secret1	29238	1			T4	27		T5	4		T6	17
secret0	43871	1			T4	60		T5	3		T6	32
hw_cfg1	39299	1			T4	27		T5	2		T6	13
hw_cfg0	22682	1			T4	25		T6	29		T10	20
rot_creator_auth_state	24131	1			T4	17		T5	2		T6	31
rot_creator_auth_codesign	23352	1			T3	2		T4	41		T5	3
owner_sw_cfg	23171	1			T3	1		T4	29		T5	4
creator_sw_cfg	20854	1			T4	36		T5	2		T6	38
vendor_test	27988	1			T4	40		T5	13		T6	51

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2858	1			T3	272		T97	237		T150	63
fsm_err	secret1	3721	1			T117	43		T211	49		T361	241
fsm_err	secret0	5838	1			T4	24		T7	2		T112	192
fsm_err	hw_cfg1	6207	1			T274	291		T169	77		T277	162
fsm_err	hw_cfg0	5927	1			T159	33		T260	395		T252	79
fsm_err	rot_creator_auth_state	5320	1			T276	127		T362	227		T363	222
fsm_err	rot_creator_auth_codesign	4671	1			T250	184		T364	1		T365	603
fsm_err	owner_sw_cfg	4586	1			T254	347		T190	446		T366	151
fsm_err	creator_sw_cfg	3544	1			T8	369		T223	195		T180	2
fsm_err	vendor_test	10665	1			T5	12		T11	54		T12	6
access_err	life_cycle	767	1			T13	11		T14	5		T15	17
access_err	secret2	10792	1			T4	31		T6	17		T10	7
access_err	secret1	5687	1			T5	3		T6	9		T10	31
access_err	secret0	4767	1			T4	2		T5	2		T6	18
access_err	hw_cfg1	1224	1			T4	2		T5	2		T6	1
access_err	hw_cfg0	1914	1			T6	7		T10	2		T49	6
access_err	rot_creator_auth_state	6145	1			T4	5		T6	24		T10	22
access_err	rot_creator_auth_codesign	8286	1			T4	15		T5	1		T6	34
access_err	owner_sw_cfg	7229	1			T4	12		T5	2		T6	33
access_err	creator_sw_cfg	7905	1			T4	24		T6	17		T10	23
access_err	vendor_test	7271	1			T4	22		T6	23		T10	13
write_blank_err	secret2	8	1			T15	1		T144	1		T367	1
write_blank_err	secret1	29	1			T128	1		T13	1		T232	1
write_blank_err	secret0	65	1			T7	1		T15	1		T114	2
write_blank_err	hw_cfg1	66	1			T8	1		T116	1		T274	1
write_blank_err	hw_cfg0	6	1			T368	1		T369	1		T145	1
write_blank_err	rot_creator_auth_state	138	1			T8	1		T14	1		T15	1
write_blank_err	rot_creator_auth_codesign	61	1			T114	3		T370	2		T100	1
write_blank_err	owner_sw_cfg	25	1			T15	2		T100	1		T371	1
write_blank_err	creator_sw_cfg	32	1			T15	1		T100	2		T372	1
write_blank_err	vendor_test	29	1			T370	1		T371	1		T71	1
ecc_uncorr_err	secret2	2971	1			T139	37		T15	138		T373	45
ecc_uncorr_err	secret1	9984	1			T128	431		T13	209		T109	4
ecc_uncorr_err	secret0	24319	1			T7	123		T139	35		T176	30
ecc_uncorr_err	hw_cfg1	20909	1			T138	68		T8	155		T116	682
ecc_uncorr_err	hw_cfg0	2291	1			T138	51		T139	72		T176	15
ecc_uncorr_err	rot_creator_auth_state	3988	1			T139	39		T14	268		T374	201
ecc_uncorr_err	rot_creator_auth_codesign	848	1			T139	55		T109	3		T211	50
ecc_uncorr_err	owner_sw_cfg	2115	1			T375	513		T376	136		T293	25
ecc_uncorr_err	creator_sw_cfg	831	1			T138	67		T176	23		T109	2
ecc_corr_err	secret2	78	1			T176	1		T35	1		T70	12
ecc_corr_err	secret1	157	1			T138	1		T139	3		T109	1
ecc_corr_err	secret0	117	1			T139	5		T114	1		T35	1
ecc_corr_err	hw_cfg1	245	1			T138	4		T176	2		T70	6
ecc_corr_err	hw_cfg0	212	1			T35	3		T70	7		T368	2
ecc_corr_err	rot_creator_auth_state	133	1			T11	1		T138	1		T176	3
ecc_corr_err	rot_creator_auth_codesign	98	1			T11	2		T109	1		T180	1
ecc_corr_err	owner_sw_cfg	97	1			T176	2		T70	1		T208	7
ecc_corr_err	creator_sw_cfg	113	1			T5	2		T139	1		T176	3
no_err	secret2	5419	1			T4	1		T5	1		T6	1
no_err	secret1	9660	1			T4	27		T5	1		T6	8
no_err	secret0	8765	1			T4	34		T5	1		T6	14
no_err	hw_cfg1	10648	1			T4	25		T6	12		T10	23
no_err	hw_cfg0	12332	1			T4	25		T6	22		T10	18
no_err	rot_creator_auth_state	8407	1			T4	12		T5	2		T6	7
no_err	rot_creator_auth_codesign	9388	1			T3	2		T4	26		T5	2
no_err	owner_sw_cfg	9119	1			T3	1		T4	17		T5	2
no_err	creator_sw_cfg	8429	1			T4	12		T6	21		T10	22
no_err	vendor_test	10023	1			T4	18		T5	1		T6	28

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded