Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	51576	1			T7	487		T27	65		T96	78
access_err	60797	1			T1	10		T2	29		T4	5
write_blank_err	460	1			T1	1		T6	1		T13	1
ecc_uncorr_err	68520	1			T1	607		T11	17		T6	677
ecc_corr_err	1235	1			T11	1		T45	6		T27	6
no_err	89882	1			T1	23		T2	45		T3	68

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	910	1			T6	7		T13	15		T14	4
secret2	25597	1			T1	2		T2	12		T3	4
secret1	27232	1			T1	615		T2	6		T3	15
secret0	39317	1			T1	4		T2	9		T3	2
hw_cfg1	34880	1			T2	5		T3	1		T4	6
hw_cfg0	25022	1			T1	2		T2	4		T3	12
rot_creator_auth_state	22451	1			T1	5		T2	7		T3	5
rot_creator_auth_codesign	20441	1			T1	3		T2	7		T3	8
owner_sw_cfg	20719	1			T1	4		T2	8		T3	10
creator_sw_cfg	21614	1			T1	2		T2	11		T3	8
vendor_test	34287	1			T1	4		T2	5		T3	3

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3844	1			T218	267		T294	446		T351	354
fsm_err	secret1	4468	1			T93	60		T227	64		T352	294
fsm_err	secret0	4444	1			T16	7		T215	676		T353	191
fsm_err	hw_cfg1	3810	1			T96	78		T274	264		T354	543
fsm_err	hw_cfg0	3800	1			T90	99		T76	97		T132	12
fsm_err	rot_creator_auth_state	3012	1			T14	44		T93	210		T342	219
fsm_err	rot_creator_auth_codesign	3509	1			T17	447		T133	81		T134	70
fsm_err	owner_sw_cfg	3476	1			T7	487		T76	440		T249	451
fsm_err	creator_sw_cfg	4122	1			T248	29		T100	181		T198	59
fsm_err	vendor_test	17091	1			T27	65		T75	204		T93	78
access_err	life_cycle	910	1			T6	7		T13	15		T14	4
access_err	secret2	10516	1			T1	2		T2	11		T5	19
access_err	secret1	5801	1			T2	5		T12	32		T27	1
access_err	secret0	4615	1			T2	8		T5	1		T12	11
access_err	hw_cfg1	1239	1			T5	1		T12	3		T45	1
access_err	hw_cfg0	2250	1			T2	3		T12	5		T27	5
access_err	rot_creator_auth_state	5831	1			T1	3		T2	1		T4	2
access_err	rot_creator_auth_codesign	7467	1			T1	1		T5	3		T12	25
access_err	owner_sw_cfg	7093	1			T1	2		T5	2		T12	5
access_err	creator_sw_cfg	7733	1			T1	1		T2	1		T5	7
access_err	vendor_test	7342	1			T1	1		T4	3		T5	4
write_blank_err	secret2	13	1			T197	1		T213	1		T242	1
write_blank_err	secret1	23	1			T1	1		T76	1		T18	1
write_blank_err	secret0	59	1			T13	1		T76	1		T100	1
write_blank_err	hw_cfg1	56	1			T14	1		T90	1		T93	2
write_blank_err	hw_cfg0	17	1			T6	1		T226	1		T355	1
write_blank_err	rot_creator_auth_state	145	1			T76	1		T100	1		T196	1
write_blank_err	rot_creator_auth_codesign	69	1			T238	3		T213	2		T242	4
write_blank_err	owner_sw_cfg	39	1			T196	1		T226	2		T238	4
write_blank_err	creator_sw_cfg	10	1			T242	1		T356	1		T345	1
write_blank_err	vendor_test	29	1			T76	2		T169	1		T355	2
ecc_uncorr_err	secret2	5823	1			T197	250		T134	67		T194	24
ecc_uncorr_err	secret1	7892	1			T1	607		T45	2		T76	354
ecc_uncorr_err	secret0	21813	1			T11	17		T13	362		T76	289
ecc_uncorr_err	hw_cfg1	18794	1			T45	8		T14	510		T90	199
ecc_uncorr_err	hw_cfg0	6473	1			T6	677		T133	67		T134	46
ecc_uncorr_err	rot_creator_auth_state	4796	1			T45	4		T132	10		T100	155
ecc_uncorr_err	rot_creator_auth_codesign	563	1			T132	22		T183	63		T181	62
ecc_uncorr_err	owner_sw_cfg	949	1			T132	7		T134	48		T183	63
ecc_uncorr_err	creator_sw_cfg	1417	1			T133	72		T183	68		T181	70
ecc_corr_err	secret2	84	1			T11	1		T132	1		T134	2
ecc_corr_err	secret1	85	1			T45	2		T75	4		T36	1
ecc_corr_err	secret0	110	1			T75	2		T46	2		T36	10
ecc_corr_err	hw_cfg1	271	1			T75	9		T76	1		T46	4
ecc_corr_err	hw_cfg0	226	1			T27	1		T75	19		T36	11
ecc_corr_err	rot_creator_auth_state	111	1			T75	2		T46	2		T36	5
ecc_corr_err	rot_creator_auth_codesign	112	1			T27	3		T75	2		T36	1
ecc_corr_err	owner_sw_cfg	123	1			T45	4		T27	1		T75	13
ecc_corr_err	creator_sw_cfg	113	1			T27	1		T46	1		T36	2
no_err	secret2	5317	1			T2	1		T3	4		T4	10
no_err	secret1	8963	1			T1	7		T2	1		T3	15
no_err	secret0	8276	1			T1	4		T2	1		T3	2
no_err	hw_cfg1	10710	1			T2	5		T3	1		T4	6
no_err	hw_cfg0	12256	1			T1	2		T2	1		T3	12
no_err	rot_creator_auth_state	8556	1			T1	2		T2	6		T3	5
no_err	rot_creator_auth_codesign	8721	1			T1	2		T2	7		T3	8
no_err	owner_sw_cfg	9039	1			T1	2		T2	8		T3	10
no_err	creator_sw_cfg	8219	1			T1	1		T2	10		T3	8
no_err	vendor_test	9825	1			T1	3		T2	5		T3	3

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded