Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

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Summary for Group tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
flash_data_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
flash_data_req_during_lc_esc	2	0	2	100.00	100	1	1	0
flash_data_req_during_otbn_req	2	0	2	100.00	100	1	1	2
flash_data_req_during_otp_idle	2	0	2	100.00	100	1	1	2
flash_data_req_during_sram_0_req	2	0	2	100.00	100	1	1	2
flash_data_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable flash_data_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12812

1

T4

15

T5

28

T6

3

auto[1]

858

1

T4

3

T6

3

T17

7

---

Summary for Variable flash_data_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for flash_data_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

13640

1

T4

18

T5

28

T6

6

lc_esc_on

30

1

T161

1

T127

1

T20

1

---

Summary for Variable flash_data_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12802

1

T4

14

T5

28

T6

6

auto[1]

868

1

T4

4

T17

2

T8

14

---

Summary for Variable flash_data_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1887

1

T4

3

T6

2

T31

1

auto[1]

11783

1

T4

15

T5

28

T6

4

---

Summary for Variable flash_data_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11381

1

T4

17

T5

27

T6

6

auto[1]

2289

1

T4

1

T5

1

T17

5

---

Summary for Variable flash_data_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13213

1

T4

18

T5

28

T6

5

auto[1]

457

1

T6

1

T17

5

T20

3