Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	49029	1			T2	552		T5	76		T33	71
access_err	66254	1			T3	1		T4	149		T6	6
write_blank_err	472	1			T7	11		T8	1		T128	1
ecc_uncorr_err	67728	1			T5	616		T7	625		T8	482
ecc_corr_err	1776	1			T5	21		T33	14		T55	79
no_err	95802	1			T3	22		T4	156		T5	42

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	752	1			T7	10		T8	4		T9	13
secret2	24959	1			T2	552		T4	24		T5	143
secret1	31792	1			T3	2		T4	22		T5	80
secret0	38029	1			T3	5		T4	27		T5	6
hw_cfg1	36041	1			T3	4		T4	20		T5	4
hw_cfg0	24718	1			T3	6		T4	36		T5	75
rot_creator_auth_state	24986	1			T4	30		T5	138		T6	2
rot_creator_auth_codesign	23456	1			T3	5		T4	39		T5	82
owner_sw_cfg	20812	1			T4	37		T5	2		T6	12
creator_sw_cfg	22822	1			T4	43		T5	209		T13	19
vendor_test	32694	1			T3	1		T4	27		T5	16

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	5129	1			T2	552		T165	233		T259	242
fsm_err	secret1	6610	1			T169	45		T152	112		T261	75
fsm_err	secret0	2420	1			T156	75		T354	13		T189	48
fsm_err	hw_cfg1	1880	1			T20	174		T355	12		T356	347
fsm_err	hw_cfg0	4611	1			T127	460		T357	49		T262	37
fsm_err	rot_creator_auth_state	3975	1			T234	47		T237	11		T238	30
fsm_err	rot_creator_auth_codesign	3656	1			T96	127		T221	49		T358	45
fsm_err	owner_sw_cfg	2209	1			T161	41		T219	6		T220	21
fsm_err	creator_sw_cfg	4230	1			T5	76		T247	201		T359	3
fsm_err	vendor_test	14309	1			T33	71		T70	181		T77	39
access_err	life_cycle	752	1			T7	10		T8	4		T9	13
access_err	secret2	11498	1			T4	13		T6	1		T31	4
access_err	secret1	6485	1			T33	13		T17	10		T19	2
access_err	secret0	4924	1			T4	9		T6	4		T31	5
access_err	hw_cfg1	1305	1			T3	1		T4	5		T33	3
access_err	hw_cfg0	2288	1			T4	1		T31	2		T32	3
access_err	rot_creator_auth_state	6471	1			T4	14		T31	3		T17	7
access_err	rot_creator_auth_codesign	8726	1			T4	27		T31	1		T33	1
access_err	owner_sw_cfg	7473	1			T4	32		T6	1		T33	6
access_err	creator_sw_cfg	8389	1			T4	30		T33	7		T17	10
access_err	vendor_test	7943	1			T4	18		T31	1		T33	4
write_blank_err	secret2	6	1			T360	1		T361	1		T362	1
write_blank_err	secret1	25	1			T363	1		T120	1		T245	1
write_blank_err	secret0	53	1			T15	1		T171	1		T223	1
write_blank_err	hw_cfg1	73	1			T9	1		T170	1		T247	1
write_blank_err	hw_cfg0	12	1			T7	1		T247	1		T223	1
write_blank_err	rot_creator_auth_state	167	1			T7	3		T8	1		T128	1
write_blank_err	rot_creator_auth_codesign	77	1			T247	2		T245	4		T364	1
write_blank_err	owner_sw_cfg	22	1			T7	3		T97	2		T185	1
write_blank_err	creator_sw_cfg	13	1			T7	4		T365	1		T294	1
write_blank_err	vendor_test	24	1			T15	1		T185	1		T366	1
ecc_uncorr_err	secret2	2380	1			T5	141		T169	105		T360	99
ecc_uncorr_err	secret1	9226	1			T5	75		T363	142		T120	107
ecc_uncorr_err	secret0	21721	1			T15	484		T171	595		T223	389
ecc_uncorr_err	hw_cfg1	21156	1			T9	376		T170	599		T237	11
ecc_uncorr_err	hw_cfg0	4417	1			T5	70		T7	625		T169	112
ecc_uncorr_err	rot_creator_auth_state	5129	1			T5	127		T8	482		T128	441
ecc_uncorr_err	rot_creator_auth_codesign	1484	1			T5	73		T219	12		T220	24
ecc_uncorr_err	owner_sw_cfg	1269	1			T169	155		T367	44		T218	53
ecc_uncorr_err	creator_sw_cfg	946	1			T5	130		T169	50		T368	16
ecc_corr_err	secret2	135	1			T55	3		T176	1		T73	7
ecc_corr_err	secret1	147	1			T5	4		T33	1		T55	3
ecc_corr_err	secret0	186	1			T5	4		T55	4		T169	2
ecc_corr_err	hw_cfg1	367	1			T33	1		T55	21		T169	2
ecc_corr_err	hw_cfg0	329	1			T5	1		T55	19		T169	2
ecc_corr_err	rot_creator_auth_state	181	1			T5	5		T33	3		T55	11
ecc_corr_err	rot_creator_auth_codesign	140	1			T5	7		T33	9		T55	10
ecc_corr_err	owner_sw_cfg	140	1			T55	7		T169	1		T237	1
ecc_corr_err	creator_sw_cfg	151	1			T55	1		T169	1		T82	4
no_err	secret2	5811	1			T4	11		T5	2		T6	2
no_err	secret1	9299	1			T3	2		T4	22		T5	1
no_err	secret0	8725	1			T3	5		T4	18		T5	2
no_err	hw_cfg1	11260	1			T3	3		T4	15		T5	4
no_err	hw_cfg0	13061	1			T3	6		T4	35		T5	4
no_err	rot_creator_auth_state	9063	1			T4	16		T5	6		T6	2
no_err	rot_creator_auth_codesign	9373	1			T3	5		T4	12		T5	2
no_err	owner_sw_cfg	9699	1			T4	5		T5	2		T6	11
no_err	creator_sw_cfg	9093	1			T4	13		T5	3		T13	19
no_err	vendor_test	10418	1			T3	1		T4	9		T5	16

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded