SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 22 | 0 | 22 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
creator_sw_cfg_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
hw_cfg0_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
hw_cfg1_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
lc_esc | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
owner_sw_cfg_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
rot_creator_auth_codesign_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
rot_creator_auth_state_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
secret0_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
secret1_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
secret2_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
vendor_test_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7795 | 1 | T1 | 4 | T2 | 4 | T3 | 6 | ||||
auto[1] | 4796 | 1 | T4 | 8 | T6 | 6 | T31 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7676 | 1 | T1 | 4 | T2 | 4 | T3 | 5 | ||||
auto[1] | 4915 | 1 | T3 | 1 | T4 | 6 | T12 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7580 | 1 | T1 | 4 | T2 | 4 | T3 | 6 | ||||
auto[1] | 5011 | 1 | T4 | 8 | T12 | 1 | T6 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 12543 | 1 | T1 | 4 | T2 | 4 | T3 | 6 | ||||
auto[1] | 48 | 1 | T77 | 1 | T105 | 1 | T215 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 9636 | 1 | T1 | 4 | T2 | 4 | T3 | 6 | ||||
auto[1] | 2955 | 1 | T4 | 8 | T31 | 7 | T16 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7955 | 1 | T1 | 4 | T2 | 4 | T3 | 6 | ||||
auto[1] | 4636 | 1 | T4 | 8 | T31 | 7 | T32 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 10411 | 1 | T1 | 4 | T2 | 4 | T3 | 6 | ||||
auto[1] | 2180 | 1 | T6 | 6 | T32 | 6 | T77 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7624 | 1 | T1 | 4 | T2 | 4 | T3 | 5 | ||||
auto[1] | 4967 | 1 | T3 | 1 | T4 | 6 | T12 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7710 | 1 | T1 | 4 | T2 | 4 | T3 | 6 | ||||
auto[1] | 4881 | 1 | T12 | 1 | T6 | 4 | T13 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 8859 | 1 | T1 | 4 | T2 | 4 | T3 | 6 | ||||
auto[1] | 3732 | 1 | T12 | 1 | T6 | 6 | T31 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7815 | 1 | T1 | 4 | T2 | 4 | T3 | 5 | ||||
auto[1] | 4776 | 1 | T3 | 1 | T4 | 8 | T6 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |