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Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 14964 1 T1 21 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 14964 1 T1 21 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 10683 1 T1 14 T2 2 T3 3
true 17419 1 T1 29 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 11666 1 T1 17 T2 2 T3 3
true 17472 1 T1 29 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 80 1 T94 2 T125 2 T127 2
others[1] 104 1 T16 2 T89 2 T67 8
others[2] 112 1 T28 2 T29 2 T67 2
others[3] 90 1 T98 2 T125 4 T127 2
others[4] 120 1 T95 2 T67 2 T98 2
others[5] 86 1 T5 2 T102 2 T98 2
others[6] 112 1 T67 6 T125 2 T127 2
others[7] 122 1 T27 4 T29 2 T89 2
false 14964 1 T1 21 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 98 1 T67 6 T98 4 T178 2
others[1] 108 1 T16 2 T29 2 T96 2
others[2] 92 1 T94 2 T67 6 T178 4
others[3] 98 1 T29 2 T102 2 T67 2
others[4] 96 1 T101 2 T125 2 T127 2
others[5] 96 1 T68 2 T127 2 T177 2
others[6] 104 1 T94 4 T89 2 T125 2
others[7] 110 1 T28 2 T16 2 T95 2
false 14964 1 T1 21 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T29 2 T98 2 T127 2
others[1] 124 1 T94 2 T68 2 T96 2
others[2] 108 1 T94 2 T67 2 T98 2
others[3] 96 1 T5 2 T67 2 T178 2
others[4] 96 1 T29 2 T67 6 T353 2
others[5] 80 1 T125 2 T126 2 T71 4
others[6] 90 1 T327 2 T125 4 T127 2
others[7] 142 1 T92 2 T16 2 T94 2
false 14964 1 T1 21 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 64 1 T28 2 T125 4 T178 2
others[1] 72 1 T96 2 T67 2 T127 2
others[2] 42 1 T95 2 T67 2 T132 2
others[3] 80 1 T67 2 T127 6 T178 4
others[4] 80 1 T67 2 T300 2 T71 2
others[5] 62 1 T127 4 T354 2 T322 2
others[6] 80 1 T27 2 T16 4 T102 2
others[7] 86 1 T5 2 T16 2 T125 2
false 14964 1 T1 21 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 86 1 T28 2 T16 2 T96 4
others[1] 74 1 T96 2 T67 2 T236 2
others[2] 84 1 T67 2 T125 2 T127 2
others[3] 98 1 T28 2 T105 2 T67 8
others[4] 76 1 T105 2 T67 2 T127 2
others[5] 78 1 T5 2 T127 2 T128 2
others[6] 102 1 T102 2 T67 4 T126 2
others[7] 104 1 T29 2 T67 4 T98 2
false 14964 1 T1 21 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 36 1 T68 2 T29 4 T71 2
others[1] 38 1 T105 4 T177 2 T355 2
others[2] 56 1 T128 2 T236 2 T356 2
others[3] 42 1 T178 2 T71 2 T236 2
others[4] 34 1 T67 4 T125 2 T356 2
others[5] 28 1 T29 2 T71 2 T157 4
others[6] 30 1 T178 2 T211 4 T217 2
others[7] 44 1 T68 2 T127 2 T211 4
false 14964 1 T1 21 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 92 1 T95 4 T29 4 T67 2
others[1] 110 1 T98 2 T46 2 T178 4
others[2] 106 1 T92 2 T94 2 T67 2
others[3] 98 1 T16 2 T96 2 T67 2
others[4] 106 1 T67 4 T98 2 T127 2
others[5] 88 1 T96 2 T98 4 T46 2
others[6] 84 1 T97 2 T357 2 T71 2
others[7] 106 1 T93 2 T125 6 T127 2
false 14964 1 T1 21 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 108 1 T67 4 T177 2 T300 2
others[1] 100 1 T96 2 T125 2 T126 2
others[2] 90 1 T28 2 T29 2 T97 2
others[3] 104 1 T178 2 T55 2 T71 4
others[4] 120 1 T96 2 T67 4 T127 2
others[5] 100 1 T28 2 T67 2 T98 4
others[6] 96 1 T29 2 T98 2 T177 2
others[7] 92 1 T96 2 T178 6 T71 4
false 14964 1 T1 21 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T5 2 T28 2 T68 2
others[1] 108 1 T5 2 T89 2 T67 2
others[2] 102 1 T68 2 T55 2 T71 2
others[3] 90 1 T67 2 T98 2 T300 2
others[4] 100 1 T29 2 T102 2 T89 4
others[5] 88 1 T96 4 T128 2 T177 2
others[6] 94 1 T27 2 T92 2 T95 2
others[7] 110 1 T28 2 T94 2 T67 4
false 14964 1 T1 21 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 106 1 T27 4 T67 4 T46 2
others[1] 90 1 T101 2 T102 2 T178 2
others[2] 70 1 T67 2 T125 2 T127 2
others[3] 98 1 T28 2 T94 2 T95 2
others[4] 118 1 T68 2 T29 2 T102 2
others[5] 100 1 T94 2 T89 2 T125 4
others[6] 94 1 T27 2 T92 2 T67 4
others[7] 110 1 T67 4 T98 2 T177 2
false 14964 1 T1 21 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 88 1 T27 2 T96 2 T67 10
others[1] 96 1 T67 4 T125 2 T128 2
others[2] 96 1 T94 2 T101 2 T67 6
others[3] 100 1 T95 2 T96 2 T89 2
others[4] 76 1 T27 2 T28 2 T67 12
others[5] 86 1 T67 2 T125 2 T211 2
others[6] 98 1 T92 2 T29 2 T96 2
others[7] 116 1 T5 2 T16 2 T67 6
false 14964 1 T1 21 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 31 1 T66 2 T178 2 T314 1
others[1] 27 1 T8 1 T314 1 T243 1
others[2] 40 1 T6 1 T17 2 T358 1
others[3] 33 1 T273 1 T315 2 T359 2
others[4] 23 1 T17 1 T211 2 T243 1
others[5] 40 1 T65 1 T215 1 T270 2
others[6] 30 1 T6 1 T68 2 T97 4
others[7] 38 1 T6 1 T8 1 T127 2
false 14964 1 T1 21 T2 5 T3 3
true 2528 1 T9 1 T5 8 T6 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 27 1 T314 1 T273 1 T154 2
others[1] 28 1 T6 2 T8 1 T314 1
others[2] 47 1 T6 1 T66 1 T127 2
others[3] 36 1 T17 1 T68 2 T243 1
others[4] 36 1 T8 1 T97 2 T215 1
others[5] 32 1 T97 2 T65 1 T66 1
others[6] 28 1 T270 2 T240 2 T121 2
others[7] 29 1 T17 2 T358 1 T314 1
false 12107 1 T1 17 T2 2 T3 3
true 19949 1 T1 29 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T5 2 T102 2 T67 4
others[1] 104 1 T67 6 T125 2 T127 2
others[2] 100 1 T67 4 T127 2 T178 6
others[3] 110 1 T16 2 T94 2 T95 2
others[4] 100 1 T67 4 T98 2 T125 2
others[5] 80 1 T27 2 T29 2 T125 2
others[6] 114 1 T28 2 T29 2 T98 2
others[7] 128 1 T27 2 T89 2 T118 2
false 8078 1 T1 17 T2 2 T3 3
true 17517 1 T1 29 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T29 2 T67 2 T127 2
others[1] 102 1 T16 2 T94 2 T29 2
others[2] 100 1 T94 2 T95 2 T102 2
others[3] 98 1 T16 2 T94 2 T29 2
others[4] 90 1 T68 2 T67 2 T98 2
others[5] 86 1 T67 2 T98 2 T125 2
others[6] 108 1 T101 2 T127 2 T55 2
others[7] 128 1 T28 2 T67 4 T177 2
false 7115 1 T1 14 T2 1 T3 1
true 17295 1 T1 29 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 120 1 T94 2 T67 2 T118 2
others[1] 124 1 T92 2 T94 2 T67 2
others[2] 98 1 T89 2 T125 4 T127 6
others[3] 106 1 T16 2 T94 2 T67 6
others[4] 104 1 T68 2 T96 2 T67 2
others[5] 78 1 T67 4 T327 2 T126 2
others[6] 92 1 T96 2 T67 2 T127 4
others[7] 98 1 T5 2 T29 4 T67 2
false 7554 1 T1 17 T2 2 T3 1
true 17288 1 T1 29 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 38 1 T8 1 T17 2 T66 1
others[1] 24 1 T67 2 T314 1 T360 2
others[2] 49 1 T105 2 T17 2 T215 1
others[3] 30 1 T14 1 T240 1 T361 1
others[4] 29 1 T28 2 T240 1 T121 2
others[5] 32 1 T6 1 T66 2 T240 1
others[6] 26 1 T6 1 T8 1 T17 1
others[7] 35 1 T66 1 T271 1 T109 2
false 12052 1 T1 17 T2 2 T3 3
true 19897 1 T1 29 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 66 1 T67 4 T178 2 T71 2
others[1] 76 1 T5 2 T27 2 T102 2
others[2] 66 1 T16 2 T67 2 T127 6
others[3] 62 1 T67 2 T121 2 T362 2
others[4] 68 1 T96 2 T127 2 T300 2
others[5] 70 1 T16 4 T67 2 T178 2
others[6] 60 1 T125 4 T127 4 T300 2
others[7] 98 1 T28 2 T95 2 T125 2
false 9330 1 T1 17 T2 1 T3 3
true 17512 1 T1 29 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 32 1 T66 1 T271 1 T358 1
others[1] 28 1 T6 1 T14 1 T178 2
others[2] 24 1 T8 1 T97 2 T215 1
others[3] 35 1 T6 1 T17 1 T361 1
others[4] 34 1 T300 2 T358 1 T240 1
others[5] 29 1 T17 1 T66 1 T215 1
others[6] 36 1 T6 1 T17 1 T65 1
others[7] 34 1 T8 1 T67 2 T215 1
false 12005 1 T1 17 T2 2 T3 3
true 19909 1 T1 29 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 102 1 T105 2 T67 2 T126 2
others[1] 76 1 T96 2 T67 6 T128 2
others[2] 48 1 T67 2 T177 2 T236 2
others[3] 96 1 T28 2 T105 2 T102 2
others[4] 92 1 T96 2 T67 4 T98 2
others[5] 92 1 T16 2 T96 2 T67 6
others[6] 96 1 T28 2 T29 2 T67 4
others[7] 100 1 T5 2 T67 2 T127 2
false 8088 1 T1 17 T2 2 T3 3
true 17452 1 T1 29 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 17 1 T215 1 T271 1 T240 1
others[1] 27 1 T66 1 T271 1 T358 1
others[2] 26 1 T17 1 T215 1 T358 1
others[3] 28 1 T8 2 T17 1 T215 1
others[4] 33 1 T14 2 T66 1 T272 1
others[5] 21 1 T8 2 T17 1 T125 2
others[6] 45 1 T17 1 T215 1 T46 2
others[7] 38 1 T8 1 T66 1 T314 1
false 11964 1 T1 17 T2 2 T3 3
true 19836 1 T1 29 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 36 1 T105 2 T211 2 T355 2
others[1] 34 1 T105 2 T29 2 T211 2
others[2] 48 1 T68 2 T29 2 T128 2
others[3] 52 1 T29 2 T211 2 T71 2
others[4] 36 1 T68 2 T177 2 T363 2
others[5] 50 1 T67 2 T178 2 T211 2
others[6] 22 1 T67 2 T125 2 T236 2
others[7] 30 1 T127 2 T236 2 T223 4
false 10449 1 T1 17 T2 2 T3 3
true 17505 1 T1 29 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 94 1 T95 2 T29 2 T67 2
others[1] 96 1 T29 2 T125 2 T178 2
others[2] 100 1 T92 2 T97 2 T125 2
others[3] 96 1 T93 2 T95 2 T67 2
others[4] 78 1 T96 2 T46 2 T125 2
others[5] 100 1 T16 2 T67 4 T98 2
others[6] 108 1 T94 2 T67 2 T98 2
others[7] 118 1 T96 2 T46 2 T127 2
false 7334 1 T1 14 T2 2 T3 3
true 17280 1 T1 29 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 96 1 T28 2 T96 2 T67 2
others[1] 104 1 T67 2 T177 4 T236 2
others[2] 110 1 T96 2 T67 2 T98 4
others[3] 112 1 T28 2 T178 6 T71 2
others[4] 86 1 T177 2 T178 4 T71 2
others[5] 98 1 T29 2 T96 2 T67 2
others[6] 94 1 T125 2 T127 4 T211 2
others[7] 110 1 T29 2 T97 2 T67 2
false 7334 1 T1 14 T2 2 T3 3
true 17280 1 T1 29 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 110 1 T5 2 T94 2 T68 2
others[1] 88 1 T5 2 T89 2 T67 2
others[2] 120 1 T28 2 T101 2 T29 2
others[3] 86 1 T27 2 T92 2 T98 2
others[4] 92 1 T89 2 T67 2 T125 2
others[5] 82 1 T95 2 T96 2 T67 2
others[6] 96 1 T101 2 T98 4 T125 2
others[7] 108 1 T28 2 T68 2 T96 2
false 6587 1 T1 13 T2 1 T3 1
true 17271 1 T1 29 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 104 1 T102 2 T67 4 T98 2
others[1] 82 1 T125 2 T364 2 T177 2
others[2] 112 1 T101 2 T29 2 T102 2
others[3] 120 1 T125 2 T127 4 T178 6
others[4] 82 1 T27 4 T67 6 T98 2
others[5] 104 1 T27 2 T94 2 T68 2
others[6] 82 1 T95 2 T67 2 T127 2
others[7] 100 1 T92 2 T28 2 T94 2
false 6587 1 T1 13 T2 1 T3 1
true 17271 1 T1 29 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 70 1 T327 2 T177 2 T223 2
others[1] 62 1 T16 2 T101 2 T68 2
others[2] 90 1 T28 2 T353 2 T125 2
others[3] 82 1 T27 2 T67 2 T125 2
others[4] 74 1 T89 2 T125 4 T127 2
others[5] 54 1 T16 2 T98 2 T125 2
others[6] 72 1 T125 4 T127 2 T223 6
others[7] 102 1 T98 2 T178 4 T55 2
false 7139 1 T1 12 T2 2 T3 2
true 18707 1 T1 32 T2 6 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 66 1 T67 2 T98 2 T125 2
others[1] 76 1 T27 2 T16 2 T68 2
others[2] 68 1 T27 2 T96 2 T67 2
others[3] 72 1 T354 2 T365 2 T366 2
others[4] 62 1 T16 2 T68 2 T67 2
others[5] 60 1 T106 2 T67 4 T353 2
others[6] 90 1 T98 2 T178 2 T71 4
others[7] 48 1 T29 2 T67 2 T353 2
false 7139 1 T1 12 T2 2 T3 2
true 18707 1 T1 32 T2 6 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 38 1 T6 2 T16 2 T215 2
others[1] 27 1 T6 2 T8 1 T271 1
others[2] 31 1 T66 1 T67 2 T215 1
others[3] 25 1 T17 1 T68 2 T272 1
others[4] 26 1 T14 1 T17 1 T66 1
others[5] 34 1 T6 1 T95 2 T66 1
others[6] 30 1 T8 1 T67 2 T215 1
others[7] 53 1 T6 1 T8 3 T65 1
false 12200 1 T1 17 T2 2 T3 3
true 20015 1 T1 29 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 68 1 T92 2 T67 4 T71 4
others[1] 116 1 T67 4 T125 2 T178 2
others[2] 86 1 T28 2 T101 2 T67 4
others[3] 94 1 T96 2 T89 2 T67 12
others[4] 84 1 T16 2 T95 2 T67 8
others[5] 108 1 T5 2 T96 2 T67 2
others[6] 86 1 T27 4 T94 2 T67 4
others[7] 114 1 T29 2 T96 2 T67 6
false 8026 1 T1 17 T2 1 T3 3
true 17505 1 T1 29 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 26 1 T8 1 T66 1 T240 1
others[1] 30 1 T105 2 T215 1 T109 2
others[2] 33 1 T6 1 T28 2 T14 1
others[3] 34 1 T6 1 T121 2 T367 2
others[4] 30 1 T66 1 T270 1 T314 1
others[5] 37 1 T65 1 T271 1 T368 2
others[6] 30 1 T8 1 T17 1 T67 2
others[7] 42 1 T17 1 T66 2 T102 2
false 14964 1 T1 21 T2 5 T3 3
true 2506 1 T1 1 T9 1 T5 7

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%