Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	53846	1			T1	41		T2	18		T6	214
access_err	71090	1			T1	8		T2	4		T9	26
write_blank_err	514	1			T6	5		T7	1		T8	1
ecc_uncorr_err	78705	1			T1	57		T6	960		T7	145
ecc_corr_err	1245	1			T1	9		T6	5		T93	12
no_err	98585	1			T1	17		T2	6		T3	43

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	865	1			T6	25		T7	5		T15	3
secret2	29123	1			T1	22		T2	4		T3	4
secret1	36148	1			T1	5		T2	2		T3	1
secret0	36514	1			T1	15		T3	8		T9	9
hw_cfg1	42348	1			T1	18		T2	1		T9	8
hw_cfg0	30732	1			T1	20		T3	6		T5	56
rot_creator_auth_state	24131	1			T3	5		T9	1		T5	69
rot_creator_auth_codesign	24426	1			T1	3		T3	5		T9	6
owner_sw_cfg	22444	1			T1	16		T2	3		T3	3
creator_sw_cfg	22979	1			T1	14		T3	5		T9	18
vendor_test	34275	1			T1	19		T2	18		T3	6

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	5402	1			T107	280		T66	176		T88	71
fsm_err	secret1	3615	1			T172	15		T258	210		T321	637
fsm_err	secret0	4655	1			T1	11		T100	358		T176	190
fsm_err	hw_cfg1	4876	1			T108	360		T99	190		T219	12
fsm_err	hw_cfg0	7288	1			T14	83		T17	111		T90	66
fsm_err	rot_creator_auth_state	2193	1			T127	131		T314	473		T194	21
fsm_err	rot_creator_auth_codesign	4384	1			T6	214		T174	650		T125	148
fsm_err	owner_sw_cfg	3166	1			T1	15		T145	9		T154	49
fsm_err	creator_sw_cfg	2960	1			T188	39		T189	36		T229	55
fsm_err	vendor_test	15307	1			T1	15		T2	18		T68	4
access_err	life_cycle	865	1			T6	25		T7	5		T15	3
access_err	secret2	12220	1			T1	8		T2	4		T5	35
access_err	secret1	7353	1			T9	2		T5	29		T92	3
access_err	secret0	5567	1			T9	1		T5	21		T27	3
access_err	hw_cfg1	1450	1			T9	2		T5	2		T6	4
access_err	hw_cfg0	2547	1			T5	15		T16	5		T94	16
access_err	rot_creator_auth_state	6651	1			T5	36		T6	32		T8	25
access_err	rot_creator_auth_codesign	9007	1			T9	2		T5	50		T6	50
access_err	owner_sw_cfg	7998	1			T9	3		T5	25		T6	39
access_err	creator_sw_cfg	8983	1			T9	13		T5	50		T6	53
access_err	vendor_test	8449	1			T9	3		T5	32		T6	25
write_blank_err	secret2	15	1			T67	1		T323	1		T217	1
write_blank_err	secret1	36	1			T191	1		T125	2		T302	1
write_blank_err	secret0	46	1			T65	1		T66	1		T127	2
write_blank_err	hw_cfg1	80	1			T6	4		T7	1		T8	1
write_blank_err	hw_cfg0	20	1			T15	1		T98	1		T324	1
write_blank_err	rot_creator_auth_state	163	1			T127	1		T325	1		T302	4
write_blank_err	rot_creator_auth_codesign	61	1			T179	1		T232	2		T302	3
write_blank_err	owner_sw_cfg	37	1			T6	1		T326	1		T224	3
write_blank_err	creator_sw_cfg	10	1			T314	1		T200	5		T275	1
write_blank_err	vendor_test	46	1			T14	2		T125	1		T314	1
ecc_uncorr_err	secret2	5584	1			T1	14		T67	138		T150	10
ecc_uncorr_err	secret1	15493	1			T1	2		T191	647		T125	1002
ecc_uncorr_err	secret0	17123	1			T65	557		T66	265		T127	222
ecc_uncorr_err	hw_cfg1	23923	1			T1	14		T6	960		T7	145
ecc_uncorr_err	hw_cfg0	6905	1			T1	14		T15	689		T98	281
ecc_uncorr_err	rot_creator_auth_state	5897	1			T150	14		T167	36		T322	486
ecc_uncorr_err	rot_creator_auth_codesign	1067	1			T181	65		T150	14		T167	82
ecc_uncorr_err	owner_sw_cfg	944	1			T167	85		T194	21		T195	29
ecc_uncorr_err	creator_sw_cfg	1769	1			T1	13		T142	61		T150	5
ecc_corr_err	secret2	68	1			T93	2		T29	1		T46	2
ecc_corr_err	secret1	123	1			T93	2		T29	1		T46	1
ecc_corr_err	secret0	126	1			T1	3		T142	3		T46	1
ecc_corr_err	hw_cfg1	270	1			T1	1		T6	5		T93	4
ecc_corr_err	hw_cfg0	208	1			T1	4		T142	1		T29	13
ecc_corr_err	rot_creator_auth_state	130	1			T29	9		T46	9		T327	1
ecc_corr_err	rot_creator_auth_codesign	80	1			T1	1		T93	3		T29	5
ecc_corr_err	owner_sw_cfg	123	1			T142	3		T29	3		T46	2
ecc_corr_err	creator_sw_cfg	117	1			T93	1		T29	9		T46	6
no_err	secret2	5834	1			T3	4		T9	6		T5	7
no_err	secret1	9528	1			T1	3		T2	2		T3	1
no_err	secret0	8997	1			T1	1		T3	8		T9	8
no_err	hw_cfg1	11749	1			T1	3		T2	1		T9	6
no_err	hw_cfg0	13764	1			T1	2		T3	6		T5	41
no_err	rot_creator_auth_state	9097	1			T3	5		T9	1		T5	33
no_err	rot_creator_auth_codesign	9827	1			T1	2		T3	5		T9	4
no_err	owner_sw_cfg	10176	1			T1	1		T2	3		T3	3
no_err	creator_sw_cfg	9140	1			T1	1		T3	5		T9	5
no_err	vendor_test	10473	1			T1	4		T3	6		T9	2

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded