Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	54693	1			T109	413		T160	63		T26	186
access_err	61862	1			T1	161		T2	7		T3	28
write_blank_err	370	1			T2	2		T5	1		T105	1
ecc_uncorr_err	61374	1			T2	280		T5	396		T105	132
ecc_corr_err	1319	1			T2	8		T108	5		T110	13
no_err	88756	1			T1	119		T2	31		T3	28

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	647	1			T2	3		T5	2		T6	2
secret2	22454	1			T1	32		T2	3		T3	13
secret1	27965	1			T1	35		T2	5		T10	43
secret0	36948	1			T1	24		T3	6		T5	400
hw_cfg1	35795	1			T1	22		T2	295		T3	1
hw_cfg0	25417	1			T1	23		T2	5		T3	4
rot_creator_auth_state	21611	1			T1	36		T3	1		T5	1
rot_creator_auth_codesign	23379	1			T1	28		T2	11		T3	17
owner_sw_cfg	19618	1			T1	32		T2	3		T3	2
creator_sw_cfg	20231	1			T1	14		T3	6		T10	56
vendor_test	34309	1			T1	34		T2	3		T3	6

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3249	1			T348	16		T349	17		T350	248
fsm_err	secret1	5065	1			T247	55		T152	111		T351	339
fsm_err	secret0	5413	1			T109	413		T152	412		T352	43
fsm_err	hw_cfg1	3532	1			T160	63		T353	171		T354	214
fsm_err	hw_cfg0	6090	1			T227	98		T148	129		T121	344
fsm_err	rot_creator_auth_state	3321	1			T347	22		T273	49		T272	227
fsm_err	rot_creator_auth_codesign	5179	1			T93	48		T355	424		T254	431
fsm_err	owner_sw_cfg	2735	1			T244	547		T212	313		T121	50
fsm_err	creator_sw_cfg	3097	1			T226	116		T245	108		T175	29
fsm_err	vendor_test	17012	1			T26	186		T65	27		T67	386
access_err	life_cycle	647	1			T2	3		T5	2		T6	2
access_err	secret2	11015	1			T1	26		T2	3		T3	13
access_err	secret1	5469	1			T1	23		T10	36		T42	32
access_err	secret0	4650	1			T1	16		T10	23		T42	15
access_err	hw_cfg1	1231	1			T1	1		T10	1		T12	1
access_err	hw_cfg0	2049	1			T1	2		T10	8		T42	1
access_err	rot_creator_auth_state	5884	1			T1	24		T3	1		T10	20
access_err	rot_creator_auth_codesign	8145	1			T1	19		T3	7		T10	35
access_err	owner_sw_cfg	7162	1			T1	9		T2	1		T10	47
access_err	creator_sw_cfg	7945	1			T1	10		T3	4		T10	54
access_err	vendor_test	7665	1			T1	31		T3	3		T10	35
write_blank_err	secret2	10	1			T144	1		T223	1		T356	1
write_blank_err	secret1	21	1			T6	1		T24	1		T77	1
write_blank_err	secret0	48	1			T5	1		T24	1		T34	1
write_blank_err	hw_cfg1	75	1			T2	2		T105	1		T36	4
write_blank_err	hw_cfg0	12	1			T36	1		T357	1		T358	1
write_blank_err	rot_creator_auth_state	118	1			T36	4		T166	1		T24	1
write_blank_err	rot_creator_auth_codesign	35	1			T34	1		T152	1		T359	3
write_blank_err	owner_sw_cfg	24	1			T36	1		T152	6		T359	1
write_blank_err	creator_sw_cfg	6	1			T274	1		T360	1		T361	1
write_blank_err	vendor_test	21	1			T24	1		T359	1		T357	1
ecc_uncorr_err	secret2	3239	1			T110	66		T160	63		T362	12
ecc_uncorr_err	secret1	7991	1			T110	67		T6	570		T24	115
ecc_uncorr_err	secret0	18323	1			T5	396		T110	67		T165	42
ecc_uncorr_err	hw_cfg1	19975	1			T2	280		T105	132		T110	138
ecc_uncorr_err	hw_cfg0	4600	1			T108	44		T36	452		T160	64
ecc_uncorr_err	rot_creator_auth_state	3898	1			T108	39		T110	55		T166	612
ecc_uncorr_err	rot_creator_auth_codesign	1128	1			T110	63		T160	117		T209	46
ecc_uncorr_err	owner_sw_cfg	1159	1			T108	89		T110	66		T160	126
ecc_uncorr_err	creator_sw_cfg	1061	1			T110	75		T209	22		T93	45
ecc_corr_err	secret2	110	1			T66	2		T37	3		T363	1
ecc_corr_err	secret1	112	1			T110	2		T26	5		T66	1
ecc_corr_err	secret0	164	1			T108	1		T110	2		T160	1
ecc_corr_err	hw_cfg1	276	1			T2	8		T108	2		T110	4
ecc_corr_err	hw_cfg0	212	1			T110	2		T26	19		T66	3
ecc_corr_err	rot_creator_auth_state	133	1			T110	2		T160	3		T26	2
ecc_corr_err	rot_creator_auth_codesign	96	1			T108	1		T110	1		T160	2
ecc_corr_err	owner_sw_cfg	113	1			T160	1		T26	2		T65	2
ecc_corr_err	creator_sw_cfg	103	1			T108	1		T26	1		T37	2
no_err	secret2	4831	1			T1	6		T10	24		T12	5
no_err	secret1	9307	1			T1	12		T2	5		T10	7
no_err	secret0	8350	1			T1	8		T3	6		T5	3
no_err	hw_cfg1	10706	1			T1	21		T2	5		T3	1
no_err	hw_cfg0	12454	1			T1	21		T2	5		T3	4
no_err	rot_creator_auth_state	8257	1			T1	12		T5	1		T10	12
no_err	rot_creator_auth_codesign	8796	1			T1	9		T2	11		T3	10
no_err	owner_sw_cfg	8425	1			T1	23		T2	2		T3	2
no_err	creator_sw_cfg	8019	1			T1	4		T3	2		T10	2
no_err	vendor_test	9611	1			T1	3		T2	3		T3	3

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded