Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	51474	1			T11	147		T98	121		T6	180
access_err	65010	1			T2	73		T3	4		T4	30
write_blank_err	345	1			T4	4		T6	1		T91	1
ecc_uncorr_err	63978	1			T3	534		T4	654		T98	247
ecc_corr_err	1560	1			T3	6		T11	66		T98	7
no_err	93060	1			T2	84		T3	21		T4	69

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	602	1			T4	8		T6	5		T13	2
secret2	27190	1			T2	22		T3	2		T4	4
secret1	28931	1			T2	26		T3	70		T4	663
secret0	34436	1			T2	6		T3	134		T4	9
hw_cfg1	30273	1			T2	6		T3	67		T4	5
hw_cfg0	27186	1			T2	14		T3	3		T4	10
rot_creator_auth_state	23963	1			T2	10		T3	71		T4	10
rot_creator_auth_codesign	23800	1			T2	16		T3	68		T4	4
owner_sw_cfg	22094	1			T2	19		T3	67		T4	11
creator_sw_cfg	20992	1			T2	25		T3	74		T4	15
vendor_test	35960	1			T2	13		T3	9		T4	18

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3676	1			T105	84		T91	25		T168	18
fsm_err	secret1	4746	1			T153	1		T224	365		T359	94
fsm_err	secret0	4022	1			T91	187		T14	81		T360	78
fsm_err	hw_cfg1	2416	1			T91	64		T263	305		T361	213
fsm_err	hw_cfg0	4925	1			T91	67		T152	193		T286	94
fsm_err	rot_creator_auth_state	2485	1			T98	62		T94	56		T362	109
fsm_err	rot_creator_auth_codesign	4377	1			T98	59		T91	408		T63	58
fsm_err	owner_sw_cfg	4225	1			T6	180		T169	83		T285	49
fsm_err	creator_sw_cfg	2912	1			T83	367		T89	325		T363	239
fsm_err	vendor_test	17690	1			T11	147		T108	119		T33	30
access_err	life_cycle	602	1			T4	8		T6	5		T13	2
access_err	secret2	11465	1			T2	15		T3	2		T4	4
access_err	secret1	6253	1			T2	16		T5	1		T32	21
access_err	secret0	4668	1			T11	18		T32	9		T12	4
access_err	hw_cfg1	1339	1			T3	2		T4	1		T5	3
access_err	hw_cfg0	2184	1			T2	1		T11	5		T24	11
access_err	rot_creator_auth_state	6486	1			T2	3		T4	5		T5	69
access_err	rot_creator_auth_codesign	8057	1			T2	6		T5	55		T11	15
access_err	owner_sw_cfg	7430	1			T2	4		T5	58		T11	25
access_err	creator_sw_cfg	8438	1			T2	18		T4	7		T5	87
access_err	vendor_test	8088	1			T2	10		T4	5		T5	41
write_blank_err	secret2	19	1			T6	1		T94	1		T339	1
write_blank_err	secret1	20	1			T4	1		T243	1		T141	1
write_blank_err	secret0	40	1			T173	1		T174	1		T175	1
write_blank_err	hw_cfg1	63	1			T91	1		T13	1		T63	2
write_blank_err	hw_cfg0	19	1			T63	1		T129	1		T90	1
write_blank_err	rot_creator_auth_state	92	1			T4	2		T364	1		T94	2
write_blank_err	rot_creator_auth_codesign	52	1			T130	6		T365	1		T366	1
write_blank_err	owner_sw_cfg	18	1			T4	1		T88	1		T90	5
write_blank_err	creator_sw_cfg	8	1			T367	1		T368	2		T369	1
write_blank_err	vendor_test	14	1			T243	1		T130	1		T158	1
ecc_uncorr_err	secret2	6709	1			T6	28		T94	487		T339	222
ecc_uncorr_err	secret1	8539	1			T3	70		T4	654		T98	123
ecc_uncorr_err	secret0	16752	1			T3	134		T173	110		T174	678
ecc_uncorr_err	hw_cfg1	15031	1			T3	61		T91	311		T13	110
ecc_uncorr_err	hw_cfg0	6976	1			T98	69		T172	73		T225	17
ecc_uncorr_err	rot_creator_auth_state	6117	1			T3	68		T172	28		T364	570
ecc_uncorr_err	rot_creator_auth_codesign	2276	1			T3	64		T225	11		T370	36
ecc_uncorr_err	owner_sw_cfg	750	1			T3	65		T98	55		T342	53
ecc_uncorr_err	creator_sw_cfg	828	1			T3	72		T172	86		T370	69
ecc_corr_err	secret2	102	1			T11	6		T33	1		T114	2
ecc_corr_err	secret1	162	1			T11	12		T62	2		T225	2
ecc_corr_err	secret0	153	1			T11	2		T98	2		T33	4
ecc_corr_err	hw_cfg1	327	1			T11	9		T99	1		T33	5
ecc_corr_err	hw_cfg0	268	1			T3	3		T11	4		T99	1
ecc_corr_err	rot_creator_auth_state	147	1			T3	1		T11	9		T98	1
ecc_corr_err	rot_creator_auth_codesign	122	1			T3	1		T11	7		T98	1
ecc_corr_err	owner_sw_cfg	114	1			T11	4		T99	1		T33	2
ecc_corr_err	creator_sw_cfg	165	1			T3	1		T11	13		T98	3
no_err	secret2	5219	1			T2	7		T5	39		T10	7
no_err	secret1	9211	1			T2	10		T4	8		T5	87
no_err	secret0	8801	1			T2	6		T4	9		T5	59
no_err	hw_cfg1	11097	1			T2	6		T3	4		T4	4
no_err	hw_cfg0	12814	1			T2	13		T4	10		T5	47
no_err	rot_creator_auth_state	8636	1			T2	7		T3	2		T4	3
no_err	rot_creator_auth_codesign	8916	1			T2	10		T3	3		T4	4
no_err	owner_sw_cfg	9557	1			T2	15		T3	2		T4	10
no_err	creator_sw_cfg	8641	1			T2	7		T3	1		T4	8
no_err	vendor_test	10168	1			T2	3		T3	9		T4	13

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded