Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	49302	1			T10	445		T12	166		T100	129
access_err	59129	1			T1	120		T4	24		T5	21
write_blank_err	454	1			T7	2		T105	1		T8	5
ecc_uncorr_err	73583	1			T7	570		T105	529		T8	730
ecc_corr_err	1386	1			T132	1		T96	1		T100	1
no_err	86768	1			T1	105		T4	77		T5	28

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	650	1			T7	5		T8	4		T9	2
secret2	25135	1			T1	11		T4	15		T5	5
secret1	29759	1			T1	23		T4	8		T5	7
secret0	38213	1			T1	31		T4	6		T5	3
hw_cfg1	43655	1			T1	21		T4	5		T5	3
hw_cfg0	22547	1			T1	17		T4	12		T5	8
rot_creator_auth_state	22284	1			T1	16		T4	7		T5	2
rot_creator_auth_codesign	19525	1			T1	12		T4	10		T5	8
owner_sw_cfg	18616	1			T1	13		T4	17		T5	8
creator_sw_cfg	21125	1			T1	40		T4	11		T5	4
vendor_test	29113	1			T1	41		T4	10		T5	1

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3318	1			T13	137		T125	135		T270	261
fsm_err	secret1	7103	1			T12	166		T140	81		T141	49
fsm_err	secret0	4297	1			T205	271		T249	318		T150	8
fsm_err	hw_cfg1	4201	1			T10	445		T100	72		T244	267
fsm_err	hw_cfg0	4492	1			T100	57		T143	52		T246	73
fsm_err	rot_creator_auth_state	4146	1			T27	177		T353	410		T223	326
fsm_err	rot_creator_auth_codesign	3126	1			T151	11		T152	25		T250	85
fsm_err	owner_sw_cfg	1630	1			T163	2		T14	217		T354	71
fsm_err	creator_sw_cfg	4642	1			T20	129		T355	96		T356	251
fsm_err	vendor_test	12347	1			T66	197		T195	16		T211	15
access_err	life_cycle	650	1			T7	5		T8	4		T9	2
access_err	secret2	10653	1			T1	7		T4	8		T5	5
access_err	secret1	6069	1			T1	18		T4	3		T5	2
access_err	secret0	4498	1			T1	30		T4	4		T5	3
access_err	hw_cfg1	1251	1			T1	2		T4	3		T10	1
access_err	hw_cfg0	2162	1			T1	8		T4	1		T5	1
access_err	rot_creator_auth_state	5780	1			T1	4		T10	1		T8	41
access_err	rot_creator_auth_codesign	7158	1			T1	8		T4	2		T5	3
access_err	owner_sw_cfg	6377	1			T1	7		T4	1		T5	7
access_err	creator_sw_cfg	7414	1			T1	19		T4	1		T10	1
access_err	vendor_test	7117	1			T1	17		T4	1		T10	1
write_blank_err	secret2	15	1			T8	1		T357	1		T358	1
write_blank_err	secret1	23	1			T100	1		T224	1		T255	1
write_blank_err	secret0	60	1			T7	1		T8	1		T9	1
write_blank_err	hw_cfg1	71	1			T154	1		T13	1		T223	1
write_blank_err	hw_cfg0	10	1			T359	1		T360	1		T361	1
write_blank_err	rot_creator_auth_state	161	1			T105	1		T100	4		T153	5
write_blank_err	rot_creator_auth_codesign	41	1			T7	1		T8	3		T362	1
write_blank_err	owner_sw_cfg	26	1			T363	1		T120	3		T280	1
write_blank_err	creator_sw_cfg	24	1			T153	4		T357	2		T363	1
write_blank_err	vendor_test	23	1			T364	1		T358	2		T365	2
ecc_uncorr_err	secret2	5945	1			T8	469		T357	482		T152	29
ecc_uncorr_err	secret1	7879	1			T132	51		T100	485		T163	3
ecc_uncorr_err	secret0	21169	1			T7	570		T8	261		T132	165
ecc_uncorr_err	hw_cfg1	27558	1			T154	520		T13	606		T223	548
ecc_uncorr_err	hw_cfg0	4242	1			T132	58		T96	27		T151	14
ecc_uncorr_err	rot_creator_auth_state	4070	1			T105	529		T13	161		T150	4
ecc_uncorr_err	rot_creator_auth_codesign	699	1			T150	25		T366	26		T152	28
ecc_uncorr_err	owner_sw_cfg	1121	1			T132	58		T150	23		T152	47
ecc_uncorr_err	creator_sw_cfg	900	1			T132	56		T366	29		T151	9
ecc_corr_err	secret2	109	1			T70	3		T150	1		T164	5
ecc_corr_err	secret1	130	1			T66	1		T70	5		T150	1
ecc_corr_err	secret0	168	1			T100	1		T70	10		T150	1
ecc_corr_err	hw_cfg1	273	1			T132	1		T66	9		T70	17
ecc_corr_err	hw_cfg0	228	1			T66	1		T70	5		T52	2
ecc_corr_err	rot_creator_auth_state	129	1			T70	1		T150	2		T164	1
ecc_corr_err	rot_creator_auth_codesign	120	1			T66	2		T150	2		T163	2
ecc_corr_err	owner_sw_cfg	115	1			T66	4		T70	1		T150	2
ecc_corr_err	creator_sw_cfg	114	1			T96	1		T66	2		T70	2
no_err	secret2	5095	1			T1	4		T4	7		T6	4
no_err	secret1	8555	1			T1	5		T4	5		T5	5
no_err	secret0	8021	1			T1	1		T4	2		T10	6
no_err	hw_cfg1	10301	1			T1	19		T4	2		T5	3
no_err	hw_cfg0	11413	1			T1	9		T4	11		T5	7
no_err	rot_creator_auth_state	7998	1			T1	12		T4	7		T5	2
no_err	rot_creator_auth_codesign	8381	1			T1	4		T4	8		T5	5
no_err	owner_sw_cfg	9347	1			T1	6		T4	16		T5	1
no_err	creator_sw_cfg	8031	1			T1	21		T4	10		T5	4
no_err	vendor_test	9626	1			T1	24		T4	9		T5	1

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded