Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	51409	1			T1	271		T8	24		T210	300
access_err	65335	1			T2	29		T4	487		T7	406
write_blank_err	430	1			T4	2		T13	2		T14	4
ecc_uncorr_err	64308	1			T4	439		T13	170		T14	1187
ecc_corr_err	1202	1			T144	1		T67	3		T145	13
no_err	96467	1			T1	1		T2	24		T3	65

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	692	1			T4	15		T13	2		T14	24
secret2	25128	1			T2	10		T3	4		T4	113
secret1	28681	1			T2	5		T3	4		T4	126
secret0	39732	1			T1	271		T2	7		T3	6
hw_cfg1	36288	1			T2	4		T3	3		T4	109
hw_cfg0	25515	1			T2	3		T3	7		T4	568
rot_creator_auth_state	23401	1			T2	1		T3	9		T4	104
rot_creator_auth_codesign	24035	1			T2	9		T3	5		T4	129
owner_sw_cfg	21442	1			T2	5		T3	7		T4	102
creator_sw_cfg	21465	1			T2	7		T3	9		T4	97
vendor_test	32772	1			T1	1		T2	2		T3	11

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2021	1			T155	86		T367	66		T170	44
fsm_err	secret1	2980	1			T152	74		T153	24		T95	293
fsm_err	secret0	5750	1			T1	271		T265	563		T268	351
fsm_err	hw_cfg1	4839	1			T8	24		T169	568		T211	96
fsm_err	hw_cfg0	5208	1			T14	333		T243	109		T368	425
fsm_err	rot_creator_auth_state	4306	1			T144	35		T222	38		T369	208
fsm_err	rot_creator_auth_codesign	5589	1			T210	300		T12	451		T145	51
fsm_err	owner_sw_cfg	3145	1			T370	307		T205	67		T371	266
fsm_err	creator_sw_cfg	3347	1			T12	148		T240	137		T145	34
fsm_err	vendor_test	14224	1			T67	210		T231	27		T71	37
access_err	life_cycle	692	1			T4	15		T13	2		T14	24
access_err	secret2	11609	1			T2	7		T4	87		T7	66
access_err	secret1	6178	1			T2	3		T4	83		T7	50
access_err	secret0	4901	1			T2	6		T4	46		T7	38
access_err	hw_cfg1	1294	1			T2	1		T4	15		T7	2
access_err	hw_cfg0	2250	1			T2	3		T4	39		T7	14
access_err	rot_creator_auth_state	6233	1			T2	1		T4	40		T7	11
access_err	rot_creator_auth_codesign	8608	1			T2	3		T4	48		T7	86
access_err	owner_sw_cfg	7440	1			T2	3		T4	26		T7	51
access_err	creator_sw_cfg	8320	1			T2	2		T4	44		T7	43
access_err	vendor_test	7810	1			T4	44		T7	45		T5	7
write_blank_err	secret2	14	1			T13	1		T14	1		T15	1
write_blank_err	secret1	22	1			T14	1		T66	1		T260	1
write_blank_err	secret0	56	1			T66	1		T173	1		T246	1
write_blank_err	hw_cfg1	68	1			T66	1		T172	1		T141	2
write_blank_err	hw_cfg0	15	1			T4	1		T260	1		T372	1
write_blank_err	rot_creator_auth_state	120	1			T14	1		T15	6		T16	1
write_blank_err	rot_creator_auth_codesign	50	1			T156	1		T373	1		T374	2
write_blank_err	owner_sw_cfg	31	1			T15	1		T309	1		T362	3
write_blank_err	creator_sw_cfg	21	1			T141	1		T373	1		T375	1
write_blank_err	vendor_test	33	1			T4	1		T13	1		T14	1
ecc_uncorr_err	secret2	5862	1			T13	170		T14	589		T15	103
ecc_uncorr_err	secret1	9542	1			T14	598		T66	142		T145	55
ecc_uncorr_err	secret0	19482	1			T66	657		T145	47		T173	384
ecc_uncorr_err	hw_cfg1	18448	1			T66	467		T172	230		T141	675
ecc_uncorr_err	hw_cfg0	5061	1			T4	439		T145	51		T174	3
ecc_uncorr_err	rot_creator_auth_state	3657	1			T145	106		T183	65		T376	139
ecc_uncorr_err	rot_creator_auth_codesign	616	1			T302	64		T377	67		T378	18
ecc_uncorr_err	owner_sw_cfg	989	1			T145	53		T183	64		T221	43
ecc_uncorr_err	creator_sw_cfg	651	1			T145	55		T174	21		T378	19
ecc_corr_err	secret2	71	1			T145	2		T81	7		T113	1
ecc_corr_err	secret1	99	1			T145	2		T71	2		T26	2
ecc_corr_err	secret0	139	1			T145	3		T71	6		T26	1
ecc_corr_err	hw_cfg1	275	1			T67	2		T71	4		T141	3
ecc_corr_err	hw_cfg0	196	1			T67	1		T145	1		T26	1
ecc_corr_err	rot_creator_auth_state	105	1			T144	1		T113	1		T130	3
ecc_corr_err	rot_creator_auth_codesign	89	1			T113	3		T183	3		T120	2
ecc_corr_err	owner_sw_cfg	127	1			T145	1		T81	5		T113	4
ecc_corr_err	creator_sw_cfg	101	1			T145	4		T71	2		T130	6
no_err	secret2	5551	1			T2	3		T3	4		T4	26
no_err	secret1	9860	1			T2	2		T3	4		T4	43
no_err	secret0	9404	1			T2	1		T3	6		T4	62
no_err	hw_cfg1	11364	1			T2	3		T3	3		T4	94
no_err	hw_cfg0	12785	1			T3	7		T4	89		T7	46
no_err	rot_creator_auth_state	8980	1			T3	9		T4	64		T7	26
no_err	rot_creator_auth_codesign	9083	1			T2	6		T3	5		T4	81
no_err	owner_sw_cfg	9710	1			T2	2		T3	7		T4	76
no_err	creator_sw_cfg	9025	1			T2	5		T3	9		T4	53
no_err	vendor_test	10705	1			T1	1		T2	2		T3	11

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded