Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	49693	1			T4	596		T9	319		T18	76
access_err	60286	1			T1	2		T3	11		T4	83
write_blank_err	442	1			T6	1		T7	3		T217	1
ecc_uncorr_err	65603	1			T6	399		T113	49		T154	140
ecc_corr_err	1380	1			T113	13		T154	6		T79	53
no_err	88787	1			T1	19		T2	111		T3	23

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	680	1			T6	10		T7	4		T15	9
secret2	24055	1			T1	2		T2	14		T3	2
secret1	30091	1			T1	5		T2	5		T3	5
secret0	38448	1			T1	2		T2	9		T3	1
hw_cfg1	28917	1			T2	6		T3	9		T4	216
hw_cfg0	25562	1			T1	4		T2	8		T3	4
rot_creator_auth_state	23656	1			T2	8		T3	6		T4	43
rot_creator_auth_codesign	21720	1			T1	2		T2	11		T3	2
owner_sw_cfg	19279	1			T2	12		T3	1		T4	20
creator_sw_cfg	20600	1			T1	6		T2	14		T4	30
vendor_test	33183	1			T2	24		T3	4		T4	24

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2699	1			T22	219		T227	193		T358	26
fsm_err	secret1	3889	1			T108	107		T84	416		T206	334
fsm_err	secret0	5021	1			T4	399		T9	319		T17	301
fsm_err	hw_cfg1	2677	1			T4	197		T7	54		T21	234
fsm_err	hw_cfg0	5897	1			T116	202		T7	36		T191	21
fsm_err	rot_creator_auth_state	4404	1			T113	2		T259	637		T359	9
fsm_err	rot_creator_auth_codesign	4031	1			T18	76		T121	148		T197	54
fsm_err	owner_sw_cfg	2213	1			T360	35		T236	133		T361	66
fsm_err	creator_sw_cfg	3010	1			T154	21		T264	43		T150	57
fsm_err	vendor_test	15852	1			T77	392		T75	44		T79	54
access_err	life_cycle	680	1			T6	10		T7	4		T15	9
access_err	secret2	10765	1			T1	2		T3	1		T4	22
access_err	secret1	5635	1			T3	5		T8	1		T12	7
access_err	secret0	4558	1			T8	4		T11	1		T12	3
access_err	hw_cfg1	1272	1			T3	3		T4	1		T77	1
access_err	hw_cfg0	2113	1			T8	1		T12	1		T16	15
access_err	rot_creator_auth_state	5604	1			T3	1		T4	23		T8	11
access_err	rot_creator_auth_codesign	7853	1			T4	6		T8	5		T11	1
access_err	owner_sw_cfg	6831	1			T4	13		T8	4		T11	3
access_err	creator_sw_cfg	7627	1			T4	10		T8	4		T11	2
access_err	vendor_test	7348	1			T3	1		T4	8		T8	1
write_blank_err	secret2	15	1			T131	1		T360	1		T350	1
write_blank_err	secret1	28	1			T6	1		T362	1		T131	1
write_blank_err	secret0	51	1			T217	1		T84	1		T22	1
write_blank_err	hw_cfg1	47	1			T7	1		T15	1		T159	1
write_blank_err	hw_cfg0	13	1			T84	1		T13	1		T363	1
write_blank_err	rot_creator_auth_state	165	1			T7	2		T84	14		T118	1
write_blank_err	rot_creator_auth_codesign	52	1			T84	3		T118	6		T159	3
write_blank_err	owner_sw_cfg	33	1			T84	3		T360	1		T298	3
write_blank_err	creator_sw_cfg	14	1			T347	1		T364	4		T365	1
write_blank_err	vendor_test	24	1			T84	4		T23	1		T74	1
ecc_uncorr_err	secret2	5373	1			T360	493		T366	54		T208	34
ecc_uncorr_err	secret1	11515	1			T6	399		T113	17		T154	20
ecc_uncorr_err	secret0	20411	1			T217	378		T84	400		T158	26
ecc_uncorr_err	hw_cfg1	14239	1			T113	9		T154	15		T7	469
ecc_uncorr_err	hw_cfg0	5448	1			T113	9		T84	283		T13	417
ecc_uncorr_err	rot_creator_auth_state	4980	1			T154	20		T7	836		T118	640
ecc_uncorr_err	rot_creator_auth_codesign	932	1			T154	8		T158	20		T150	62
ecc_uncorr_err	owner_sw_cfg	893	1			T113	14		T158	23		T367	91
ecc_uncorr_err	creator_sw_cfg	1812	1			T154	77		T367	46		T368	61
ecc_corr_err	secret2	62	1			T79	3		T64	1		T58	2
ecc_corr_err	secret1	143	1			T113	2		T154	2		T79	4
ecc_corr_err	secret0	126	1			T79	5		T57	1		T64	2
ecc_corr_err	hw_cfg1	250	1			T113	5		T154	3		T79	11
ecc_corr_err	hw_cfg0	235	1			T154	1		T79	8		T144	6
ecc_corr_err	rot_creator_auth_state	134	1			T113	5		T79	5		T64	2
ecc_corr_err	rot_creator_auth_codesign	161	1			T79	12		T144	5		T158	1
ecc_corr_err	owner_sw_cfg	138	1			T113	1		T80	2		T57	1
ecc_corr_err	creator_sw_cfg	131	1			T79	5		T144	3		T57	1
no_err	secret2	5141	1			T2	14		T3	1		T4	13
no_err	secret1	8881	1			T1	5		T2	5		T4	49
no_err	secret0	8281	1			T1	2		T2	9		T3	1
no_err	hw_cfg1	10432	1			T2	6		T3	6		T4	18
no_err	hw_cfg0	11856	1			T1	4		T2	8		T3	4
no_err	rot_creator_auth_state	8369	1			T2	8		T3	5		T4	20
no_err	rot_creator_auth_codesign	8691	1			T1	2		T2	11		T3	2
no_err	owner_sw_cfg	9171	1			T2	12		T3	1		T4	7
no_err	creator_sw_cfg	8006	1			T1	6		T2	14		T4	20
no_err	vendor_test	9959	1			T2	24		T3	3		T4	16

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded