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Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 14638 1 T1 6 T2 12 T3 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 14638 1 T1 6 T2 12 T3 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 10497 1 T1 3 T2 8 T3 6
true 17070 1 T1 6 T2 12 T3 7


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 11441 1 T1 4 T2 8 T3 6
true 17130 1 T1 6 T2 12 T3 7


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 112 1 T9 2 T36 2 T65 2
others[1] 96 1 T104 2 T267 2 T257 2
others[2] 88 1 T22 2 T36 2 T65 8
others[3] 92 1 T36 4 T65 2 T93 2
others[4] 126 1 T35 2 T36 4 T72 8
others[5] 88 1 T104 2 T72 2 T147 2
others[6] 108 1 T22 2 T36 4 T65 4
others[7] 130 1 T2 2 T36 6 T65 2
false 14638 1 T1 6 T2 12 T3 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 110 1 T36 2 T65 2 T93 2
others[1] 100 1 T2 2 T36 4 T102 2
others[2] 98 1 T65 2 T72 8 T97 2
others[3] 94 1 T36 6 T65 2 T104 2
others[4] 88 1 T36 2 T65 2 T72 4
others[5] 82 1 T22 2 T104 2 T367 4
others[6] 98 1 T103 2 T72 6 T97 2
others[7] 110 1 T22 2 T36 2 T103 2
false 14638 1 T1 6 T2 12 T3 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T36 6 T72 2 T147 2
others[1] 70 1 T22 2 T36 2 T65 2
others[2] 122 1 T72 8 T96 2 T97 2
others[3] 104 1 T22 2 T36 2 T65 2
others[4] 94 1 T36 2 T93 2 T72 2
others[5] 122 1 T102 2 T65 6 T103 2
others[6] 90 1 T9 2 T65 4 T72 6
others[7] 94 1 T72 2 T97 2 T235 2
false 14638 1 T1 6 T2 12 T3 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 66 1 T36 2 T65 2 T93 2
others[1] 74 1 T106 2 T65 2 T103 2
others[2] 40 1 T72 2 T367 2 T67 2
others[3] 56 1 T36 2 T65 2 T72 6
others[4] 58 1 T9 2 T65 2 T368 2
others[5] 74 1 T36 4 T222 2 T369 2
others[6] 86 1 T36 2 T65 4 T72 4
others[7] 76 1 T77 2 T72 4 T175 2
false 14638 1 T1 6 T2 12 T3 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 94 1 T36 4 T77 2 T72 2
others[1] 90 1 T147 2 T368 2 T370 2
others[2] 90 1 T65 4 T72 6 T97 4
others[3] 116 1 T36 2 T65 6 T142 2
others[4] 96 1 T9 2 T22 2 T36 2
others[5] 70 1 T72 2 T222 2 T271 2
others[6] 102 1 T36 6 T72 6 T175 2
others[7] 146 1 T36 4 T65 4 T176 2
false 14638 1 T1 6 T2 12 T3 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 58 1 T72 2 T177 2 T271 2
others[1] 32 1 T22 2 T208 2 T371 2
others[2] 48 1 T23 2 T36 2 T65 2
others[3] 40 1 T97 2 T271 2 T300 2
others[4] 58 1 T65 2 T147 2 T97 2
others[5] 44 1 T36 2 T97 2 T177 2
others[6] 64 1 T65 2 T104 2 T72 4
others[7] 36 1 T177 2 T275 2 T228 2
false 14638 1 T1 6 T2 12 T3 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 102 1 T36 2 T65 4 T72 2
others[1] 80 1 T36 2 T93 2 T72 2
others[2] 104 1 T65 10 T72 4 T95 2
others[3] 78 1 T36 2 T72 4 T372 2
others[4] 122 1 T36 6 T65 4 T94 2
others[5] 76 1 T36 2 T183 2 T271 4
others[6] 88 1 T65 4 T93 2 T72 2
others[7] 136 1 T36 2 T65 4 T72 4
false 14638 1 T1 6 T2 12 T3 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 80 1 T35 2 T65 4 T72 4
others[1] 84 1 T94 2 T175 2 T96 2
others[2] 102 1 T1 2 T36 2 T65 8
others[3] 108 1 T36 2 T103 2 T72 8
others[4] 80 1 T2 2 T72 4 T97 2
others[5] 124 1 T22 2 T35 2 T36 2
others[6] 100 1 T9 2 T36 4 T102 2
others[7] 132 1 T36 4 T65 2 T72 2
false 14638 1 T1 6 T2 12 T3 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 74 1 T36 2 T97 4 T177 2
others[1] 88 1 T36 2 T65 2 T103 2
others[2] 70 1 T103 2 T72 6 T235 4
others[3] 106 1 T36 2 T104 2 T97 2
others[4] 88 1 T36 2 T98 2 T368 2
others[5] 100 1 T35 2 T36 2 T93 2
others[6] 92 1 T36 2 T102 2 T97 2
others[7] 104 1 T9 2 T36 2 T65 2
false 14638 1 T1 6 T2 12 T3 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 68 1 T36 4 T72 4 T97 2
others[1] 84 1 T36 2 T102 2 T65 6
others[2] 102 1 T36 2 T65 2 T72 4
others[3] 100 1 T36 4 T97 4 T373 2
others[4] 94 1 T65 2 T93 2 T94 2
others[5] 76 1 T2 2 T65 2 T93 2
others[6] 90 1 T36 2 T93 2 T72 6
others[7] 122 1 T22 2 T36 4 T102 2
false 14638 1 T1 6 T2 12 T3 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 98 1 T35 2 T65 2 T77 2
others[1] 84 1 T9 2 T97 2 T257 2
others[2] 92 1 T36 2 T65 2 T72 2
others[3] 120 1 T65 2 T103 2 T72 4
others[4] 104 1 T65 2 T72 2 T374 2
others[5] 132 1 T2 2 T36 4 T65 4
others[6] 112 1 T22 2 T36 2 T77 2
others[7] 122 1 T36 2 T72 8 T96 2
false 14638 1 T1 6 T2 12 T3 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 26 1 T94 2 T243 1 T246 1
others[1] 26 1 T243 1 T269 1 T273 1
others[2] 29 1 T15 2 T246 1 T276 1
others[3] 36 1 T21 2 T93 2 T15 1
others[4] 35 1 T21 1 T34 1 T96 2
others[5] 35 1 T273 1 T274 1 T375 2
others[6] 23 1 T21 1 T238 1 T217 1
others[7] 37 1 T34 1 T179 2 T15 1
false 14638 1 T1 6 T2 12 T3 6
true 2383 1 T1 2 T2 5 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 28 1 T34 1 T15 1 T246 1
others[1] 32 1 T96 2 T15 1 T238 1
others[2] 24 1 T21 1 T15 1 T131 1
others[3] 33 1 T243 1 T269 1 T210 2
others[4] 29 1 T210 1 T376 2 T276 1
others[5] 22 1 T34 1 T238 1 T273 3
others[6] 32 1 T94 2 T179 2 T128 1
others[7] 47 1 T21 3 T93 2 T15 1
false 11890 1 T1 5 T2 9 T3 6
true 19447 1 T1 8 T2 17 T3 9


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 106 1 T2 2 T22 2 T72 4
others[1] 114 1 T36 6 T65 6 T72 2
others[2] 98 1 T9 2 T36 2 T93 2
others[3] 106 1 T35 2 T36 10 T65 4
others[4] 82 1 T65 2 T77 2 T104 2
others[5] 92 1 T65 2 T147 2 T69 2
others[6] 104 1 T22 2 T36 2 T267 2
others[7] 138 1 T36 2 T65 4 T94 2
false 8006 1 T1 2 T2 2 T3 6
true 17168 1 T1 6 T2 12 T3 7


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 82 1 T2 2 T36 2 T65 2
others[1] 88 1 T22 2 T36 4 T102 2
others[2] 94 1 T65 2 T72 2 T97 2
others[3] 110 1 T36 4 T65 2 T72 16
others[4] 94 1 T104 2 T98 2 T235 2
others[5] 86 1 T36 4 T65 2 T124 2
others[6] 94 1 T65 4 T103 2 T72 2
others[7] 132 1 T22 2 T36 2 T94 2
false 6992 1 T1 1 T2 4 T3 6
true 16932 1 T1 6 T2 12 T3 7


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 110 1 T36 2 T65 2 T93 2
others[1] 74 1 T36 2 T72 2 T235 2
others[2] 84 1 T65 2 T72 6 T97 2
others[3] 84 1 T22 2 T36 2 T103 2
others[4] 110 1 T36 6 T65 8 T72 2
others[5] 114 1 T22 2 T72 2 T147 2
others[6] 108 1 T65 2 T72 4 T97 4
others[7] 96 1 T9 2 T102 2 T72 4
false 7501 1 T1 3 T2 2 T3 6
true 16972 1 T1 6 T2 12 T3 7


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 24 1 T3 1 T243 1 T336 1
others[1] 29 1 T72 2 T128 1 T220 2
others[2] 36 1 T3 1 T243 1 T269 1
others[3] 21 1 T377 2 T273 1 T336 1
others[4] 28 1 T65 2 T149 1 T246 1
others[5] 42 1 T34 2 T15 1 T243 1
others[6] 32 1 T21 1 T246 1 T37 2
others[7] 31 1 T34 1 T128 1 T15 1
false 11819 1 T1 5 T2 8 T3 6
true 19372 1 T1 7 T2 16 T3 9


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 58 1 T9 2 T106 2 T36 4
others[1] 88 1 T65 2 T103 2 T72 2
others[2] 64 1 T77 2 T220 4 T271 2
others[3] 68 1 T36 2 T65 2 T93 2
others[4] 52 1 T65 2 T72 2 T96 2
others[5] 74 1 T36 2 T65 4 T72 2
others[6] 68 1 T65 2 T72 4 T96 2
others[7] 58 1 T36 2 T183 2 T222 2
false 9306 1 T1 2 T2 2 T3 6
true 17144 1 T1 6 T2 12 T3 7


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 33 1 T34 2 T128 1 T210 1
others[1] 33 1 T238 1 T246 1 T67 2
others[2] 27 1 T149 1 T238 1 T246 1
others[3] 36 1 T179 2 T72 2 T97 2
others[4] 27 1 T13 1 T147 2 T128 1
others[5] 21 1 T4 1 T243 1 T273 1
others[6] 36 1 T13 1 T34 1 T269 1
others[7] 39 1 T3 1 T21 1 T128 1
false 11766 1 T1 5 T2 8 T3 6
true 19336 1 T1 8 T2 18 T3 8


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 92 1 T36 2 T65 2 T72 2
others[1] 82 1 T36 4 T97 2 T183 2
others[2] 106 1 T9 2 T22 2 T65 2
others[3] 108 1 T36 2 T72 8 T374 2
others[4] 94 1 T36 4 T65 4 T72 2
others[5] 122 1 T36 2 T65 2 T175 2
others[6] 106 1 T36 4 T65 2 T77 2
others[7] 94 1 T65 2 T72 2 T97 4
false 7955 1 T1 2 T2 2 T3 6
true 17083 1 T1 6 T2 12 T3 7


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 28 1 T21 1 T34 1 T149 1
others[1] 28 1 T246 1 T222 2 T271 2
others[2] 31 1 T149 1 T97 2 T15 1
others[3] 32 1 T36 2 T21 1 T97 2
others[4] 29 1 T13 2 T149 1 T15 1
others[5] 34 1 T21 1 T15 2 T243 1
others[6] 28 1 T15 1 T243 2 T269 1
others[7] 39 1 T103 2 T15 1 T243 1
false 11736 1 T1 5 T2 8 T3 6
true 19363 1 T1 8 T2 18 T3 9


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 54 1 T23 2 T36 2 T72 2
others[1] 48 1 T36 2 T65 2 T97 2
others[2] 42 1 T72 2 T378 2 T271 2
others[3] 34 1 T177 2 T67 2 T275 4
others[4] 48 1 T65 2 T97 2 T177 2
others[5] 46 1 T104 2 T147 2 T208 2
others[6] 52 1 T22 2 T72 2 T249 2
others[7] 56 1 T65 2 T72 2 T97 6
false 10062 1 T1 5 T2 8 T3 6
true 17136 1 T1 6 T2 12 T3 7


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 76 1 T65 4 T235 2 T177 2
others[1] 106 1 T36 4 T97 2 T379 2
others[2] 100 1 T72 2 T97 8 T367 2
others[3] 98 1 T65 2 T72 4 T235 2
others[4] 100 1 T65 4 T93 2 T94 2
others[5] 106 1 T36 2 T65 4 T72 6
others[6] 98 1 T36 6 T65 6 T93 2
others[7] 102 1 T36 4 T65 6 T72 4
false 7143 1 T1 1 T2 2 T3 6
true 16943 1 T1 6 T2 12 T3 7


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 92 1 T1 2 T36 4 T97 4
others[1] 72 1 T2 2 T9 2 T36 4
others[2] 106 1 T22 2 T36 2 T65 6
others[3] 108 1 T35 2 T65 2 T103 2
others[4] 128 1 T36 2 T65 6 T72 4
others[5] 96 1 T36 2 T102 2 T65 2
others[6] 104 1 T35 2 T103 2 T72 12
others[7] 104 1 T65 4 T72 4 T69 2
false 7143 1 T1 1 T2 2 T3 6
true 16943 1 T1 6 T2 12 T3 7


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 94 1 T36 2 T97 6 T368 2
others[1] 76 1 T36 4 T102 2 T72 2
others[2] 88 1 T72 2 T97 4 T373 2
others[3] 80 1 T36 2 T103 2 T72 2
others[4] 88 1 T9 2 T93 2 T103 2
others[5] 98 1 T36 4 T104 2 T98 2
others[6] 100 1 T35 2 T36 2 T103 2
others[7] 98 1 T65 4 T104 2 T72 2
false 6501 1 T1 3 T2 1 T3 6
true 16934 1 T1 6 T2 12 T3 7


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 88 1 T36 4 T65 4 T72 4
others[1] 102 1 T36 2 T65 2 T93 6
others[2] 64 1 T36 2 T65 2 T94 2
others[3] 74 1 T2 2 T36 8 T102 2
others[4] 122 1 T22 2 T102 2 T72 4
others[5] 72 1 T65 2 T72 2 T96 2
others[6] 86 1 T65 2 T147 2 T183 4
others[7] 128 1 T36 2 T65 2 T104 2
false 6501 1 T1 3 T2 1 T3 6
true 16934 1 T1 6 T2 12 T3 7


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 58 1 T77 2 T103 2 T72 2
others[1] 78 1 T36 2 T93 2 T72 2
others[2] 92 1 T107 2 T36 2 T102 2
others[3] 80 1 T36 4 T65 2 T97 2
others[4] 60 1 T35 2 T36 2 T65 2
others[5] 52 1 T97 2 T220 2 T67 2
others[6] 78 1 T65 2 T72 6 T147 2
others[7] 88 1 T2 2 T36 2 T77 2
false 6939 1 T1 2 T2 2 T3 5
true 18291 1 T1 6 T2 13 T3 9


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 68 1 T65 2 T93 2 T77 2
others[1] 78 1 T2 2 T65 2 T72 4
others[2] 62 1 T36 2 T177 2 T183 2
others[3] 56 1 T103 2 T96 2 T97 2
others[4] 86 1 T107 2 T72 2 T147 2
others[5] 66 1 T72 4 T222 2 T380 2
others[6] 56 1 T72 2 T226 6 T381 2
others[7] 106 1 T36 6 T65 2 T72 2
false 6939 1 T1 2 T2 2 T3 5
true 18291 1 T1 6 T2 13 T3 9


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 26 1 T4 1 T21 1 T128 1
others[1] 41 1 T4 1 T96 2 T97 2
others[2] 34 1 T34 1 T15 1 T243 1
others[3] 22 1 T13 1 T128 1 T269 1
others[4] 41 1 T3 1 T13 1 T21 1
others[5] 25 1 T21 1 T34 1 T149 1
others[6] 28 1 T72 2 T267 2 T382 2
others[7] 36 1 T4 1 T34 1 T243 1
false 11965 1 T1 5 T2 9 T3 6
true 19466 1 T1 8 T2 18 T3 8


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 92 1 T65 2 T103 2 T96 2
others[1] 122 1 T36 2 T65 4 T72 2
others[2] 100 1 T72 4 T177 4 T257 2
others[3] 102 1 T36 2 T77 2 T72 4
others[4] 148 1 T2 2 T9 2 T22 2
others[5] 112 1 T36 2 T77 2 T103 2
others[6] 78 1 T36 2 T65 2 T72 2
others[7] 110 1 T35 2 T65 2 T72 6
false 7854 1 T1 2 T2 2 T3 6
true 17128 1 T1 6 T2 12 T3 7


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 20 1 T238 1 T381 2 T217 1
others[1] 28 1 T128 1 T269 1 T210 1
others[2] 22 1 T65 2 T34 1 T15 1
others[3] 29 1 T3 1 T269 1 T377 2
others[4] 36 1 T149 1 T243 1 T269 1
others[5] 39 1 T21 1 T34 1 T72 2
others[6] 30 1 T243 1 T246 1 T383 1
others[7] 40 1 T3 1 T34 1 T15 1
false 14638 1 T1 6 T2 12 T3 6
true 2362 1 T1 1 T2 4 T3 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%