SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 22 | 0 | 22 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
creator_sw_cfg_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
hw_cfg0_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
hw_cfg1_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
lc_esc | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
owner_sw_cfg_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
rot_creator_auth_codesign_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
rot_creator_auth_state_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
secret0_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
secret1_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
secret2_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
vendor_test_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7938 | 1 | T1 | 3 | T2 | 3 | T3 | 7 | ||||
auto[1] | 4985 | 1 | T1 | 4 | T2 | 10 | T6 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7650 | 1 | T1 | 3 | T2 | 6 | T3 | 7 | ||||
auto[1] | 5273 | 1 | T1 | 4 | T2 | 7 | T6 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7698 | 1 | T1 | 5 | T2 | 3 | T3 | 7 | ||||
auto[1] | 5225 | 1 | T1 | 2 | T2 | 10 | T9 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 12884 | 1 | T1 | 7 | T2 | 13 | T3 | 7 | ||||
auto[1] | 39 | 1 | T6 | 1 | T91 | 1 | T182 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 9682 | 1 | T1 | 3 | T2 | 3 | T3 | 7 | ||||
auto[1] | 3241 | 1 | T1 | 4 | T2 | 10 | T6 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 8034 | 1 | T1 | 3 | T2 | 3 | T3 | 7 | ||||
auto[1] | 4889 | 1 | T1 | 4 | T2 | 10 | T6 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 10792 | 1 | T1 | 7 | T2 | 13 | T3 | 7 | ||||
auto[1] | 2131 | 1 | T23 | 5 | T22 | 14 | T36 | 30 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7679 | 1 | T1 | 3 | T2 | 3 | T3 | 7 | ||||
auto[1] | 5244 | 1 | T1 | 4 | T2 | 10 | T6 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7660 | 1 | T1 | 7 | T2 | 3 | T3 | 7 | ||||
auto[1] | 5263 | 1 | T2 | 10 | T9 | 10 | T23 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 8923 | 1 | T1 | 5 | T2 | 5 | T3 | 7 | ||||
auto[1] | 4000 | 1 | T1 | 2 | T2 | 8 | T12 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7824 | 1 | T1 | 3 | T2 | 3 | T3 | 7 | ||||
auto[1] | 5099 | 1 | T1 | 4 | T2 | 10 | T6 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |