Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	50854	1			T3	23		T104	50		T7	439
access_err	63174	1			T2	190		T3	1		T9	24
write_blank_err	508	1			T2	2		T6	4		T7	2
ecc_uncorr_err	81492	1			T2	815		T6	210		T7	1065
ecc_corr_err	1714	1			T163	9		T66	44		T44	49
no_err	93875	1			T2	241		T3	2		T4	59

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	828	1			T2	3		T6	5		T7	7
secret2	22327	1			T2	58		T3	1		T4	1
secret1	33905	1			T2	28		T3	23		T4	15
secret0	43887	1			T2	47		T4	3		T5	4
hw_cfg1	39939	1			T2	526		T4	4		T5	2
hw_cfg0	30550	1			T2	39		T4	5		T9	2
rot_creator_auth_state	22362	1			T2	364		T4	5		T5	2
rot_creator_auth_codesign	21930	1			T2	49		T4	6		T5	1
owner_sw_cfg	20339	1			T2	49		T4	7		T9	1
creator_sw_cfg	20928	1			T2	50		T3	2		T4	1
vendor_test	34622	1			T2	35		T4	12		T5	2

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2744	1			T203	1		T238	353		T241	247
fsm_err	secret1	5488	1			T3	23		T14	342		T200	624
fsm_err	secret0	4055	1			T199	19		T233	558		T209	111
fsm_err	hw_cfg1	4007	1			T201	85		T331	288		T332	28
fsm_err	hw_cfg0	8491	1			T104	50		T183	544		T140	12
fsm_err	rot_creator_auth_state	1373	1			T116	572		T333	57		T334	225
fsm_err	rot_creator_auth_codesign	3043	1			T335	57		T212	130		T336	223
fsm_err	owner_sw_cfg	2348	1			T132	109		T337	300		T338	159
fsm_err	creator_sw_cfg	2783	1			T91	563		T137	13		T237	159
fsm_err	vendor_test	16522	1			T7	439		T16	258		T66	359
access_err	life_cycle	828	1			T2	3		T6	5		T7	7
access_err	secret2	11264	1			T2	37		T3	1		T9	11
access_err	secret1	5851	1			T2	15		T12	1		T7	175
access_err	secret0	4737	1			T2	29		T9	5		T12	4
access_err	hw_cfg1	1253	1			T2	9		T9	1		T12	2
access_err	hw_cfg0	2081	1			T2	12		T7	41		T16	39
access_err	rot_creator_auth_state	6269	1			T2	10		T12	4		T7	90
access_err	rot_creator_auth_codesign	8118	1			T2	21		T9	3		T7	127
access_err	owner_sw_cfg	7069	1			T2	10		T9	1		T12	1
access_err	creator_sw_cfg	8025	1			T2	34		T9	3		T7	113
access_err	vendor_test	7679	1			T2	10		T6	4		T7	95
write_blank_err	secret2	6	1			T194	1		T191	1		T339	1
write_blank_err	secret1	33	1			T13	1		T147	1		T116	4
write_blank_err	secret0	70	1			T6	1		T90	1		T138	1
write_blank_err	hw_cfg1	82	1			T2	1		T7	1		T16	2
write_blank_err	hw_cfg0	20	1			T255	1		T229	1		T214	1
write_blank_err	rot_creator_auth_state	179	1			T2	1		T7	1		T16	1
write_blank_err	rot_creator_auth_codesign	60	1			T6	2		T138	1		T116	2
write_blank_err	owner_sw_cfg	18	1			T201	1		T229	1		T340	2
write_blank_err	creator_sw_cfg	6	1			T6	1		T340	1		T273	1
write_blank_err	vendor_test	34	1			T16	1		T138	2		T194	2
ecc_uncorr_err	secret2	2776	1			T194	103		T191	223		T339	345
ecc_uncorr_err	secret1	12852	1			T13	208		T132	68		T147	489
ecc_uncorr_err	secret0	25918	1			T6	210		T163	70		T90	517
ecc_uncorr_err	hw_cfg1	23461	1			T2	480		T7	370		T16	777
ecc_uncorr_err	hw_cfg0	7077	1			T163	71		T132	55		T255	376
ecc_uncorr_err	rot_creator_auth_state	5637	1			T2	335		T7	695		T163	65
ecc_uncorr_err	rot_creator_auth_codesign	1292	1			T163	68		T341	203		T342	2
ecc_uncorr_err	owner_sw_cfg	1015	1			T163	64		T132	61		T341	60
ecc_uncorr_err	creator_sw_cfg	1464	1			T132	140		T343	66		T344	33
ecc_corr_err	secret2	78	1			T66	9		T44	7		T45	4
ecc_corr_err	secret1	143	1			T44	8		T45	3		T31	2
ecc_corr_err	secret0	161	1			T66	3		T44	7		T45	8
ecc_corr_err	hw_cfg1	322	1			T163	1		T66	3		T44	9
ecc_corr_err	hw_cfg0	323	1			T66	14		T44	9		T45	8
ecc_corr_err	rot_creator_auth_state	175	1			T163	6		T66	7		T44	1
ecc_corr_err	rot_creator_auth_codesign	175	1			T66	2		T44	5		T45	1
ecc_corr_err	owner_sw_cfg	172	1			T163	2		T44	2		T31	3
ecc_corr_err	creator_sw_cfg	165	1			T66	6		T44	1		T45	4
no_err	secret2	5459	1			T2	21		T4	1		T5	8
no_err	secret1	9538	1			T2	13		T4	15		T5	4
no_err	secret0	8946	1			T2	18		T4	3		T5	4
no_err	hw_cfg1	10814	1			T2	36		T4	4		T5	2
no_err	hw_cfg0	12558	1			T2	27		T4	5		T9	2
no_err	rot_creator_auth_state	8729	1			T2	18		T4	5		T5	2
no_err	rot_creator_auth_codesign	9242	1			T2	28		T4	6		T5	1
no_err	owner_sw_cfg	9717	1			T2	39		T4	7		T11	22
no_err	creator_sw_cfg	8485	1			T2	16		T3	2		T4	1
no_err	vendor_test	10387	1			T2	25		T4	12		T5	2

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded