Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
sram_0_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
sram_0_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
sram_0_req_during_lc_esc	2	0	2	100.00	100	1	1	0
sram_0_req_during_otbn_req	2	0	2	100.00	100	1	1	2
sram_0_req_during_otp_idle	2	0	2	100.00	100	1	1	2
sram_0_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable sram_0_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_0_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12629

1

T1

6

T3

26

T4

30

auto[1]

803

1

T1

2

T3

4

T17

71

---

Summary for Variable sram_0_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_0_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12555

1

T1

7

T3

28

T4

30

auto[1]

877

1

T1

1

T3

2

T17

3

---

Summary for Variable sram_0_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sram_0_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

13413

1

T1

8

T3

30

T4

30

lc_esc_on

19

1

T110

1

T14

1

T367

1

---

Summary for Variable sram_0_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_0_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12611

1

T1

7

T3

29

T4

30

auto[1]

821

1

T1

1

T3

1

T17

1

---

Summary for Variable sram_0_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_0_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2085

1

T1

2

T3

4

T10

1

auto[1]

11347

1

T1

6

T3

26

T4

30

---

Summary for Variable sram_0_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_0_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11319

1

T1

5

T3

27

T4

15

auto[1]

2113

1

T1

3

T3

3

T4

15