Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	46474	1			T2	105		T6	236		T8	202
access_err	66067	1			T1	20		T2	16		T3	166
write_blank_err	410	1			T4	1		T5	1		T10	1
ecc_uncorr_err	67134	1			T4	390		T5	384		T10	152
ecc_corr_err	1489	1			T121	7		T111	15		T144	6
no_err	95745	1			T1	56		T2	59		T3	366

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	761	1			T4	5		T5	4		T11	2
secret2	24844	1			T1	6		T2	6		T3	48
secret1	31905	1			T1	6		T2	2		T3	54
secret0	31293	1			T1	8		T2	11		T3	45
hw_cfg1	39122	1			T1	7		T2	8		T3	41
hw_cfg0	26762	1			T1	14		T2	5		T3	39
rot_creator_auth_state	25578	1			T1	3		T2	9		T3	42
rot_creator_auth_codesign	22152	1			T1	12		T2	6		T3	85
owner_sw_cfg	21910	1			T1	9		T2	11		T3	46
creator_sw_cfg	21367	1			T1	11		T2	9		T3	82
vendor_test	31625	1			T2	113		T3	50		T4	37

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3732	1			T255	320		T14	172		T267	366
fsm_err	secret1	6164	1			T310	59		T149	273		T157	280
fsm_err	secret0	4293	1			T8	202		T10	373		T236	229
fsm_err	hw_cfg1	2745	1			T110	195		T163	216		T14	47
fsm_err	hw_cfg0	4177	1			T10	197		T153	96		T156	14
fsm_err	rot_creator_auth_state	2979	1			T144	38		T14	34		T311	189
fsm_err	rot_creator_auth_codesign	3076	1			T6	236		T197	11		T312	62
fsm_err	owner_sw_cfg	3506	1			T118	152		T144	38		T313	78
fsm_err	creator_sw_cfg	2992	1			T111	48		T314	247		T197	14
fsm_err	vendor_test	12810	1			T2	105		T9	105		T121	46
access_err	life_cycle	761	1			T4	5		T5	4		T11	2
access_err	secret2	11413	1			T1	3		T3	31		T6	1
access_err	secret1	6599	1			T1	5		T8	4		T10	16
access_err	secret0	5160	1			T1	5		T2	1		T3	1
access_err	hw_cfg1	1379	1			T1	1		T2	2		T10	5
access_err	hw_cfg0	2291	1			T1	1		T2	2		T10	6
access_err	rot_creator_auth_state	6364	1			T3	15		T4	12		T9	27
access_err	rot_creator_auth_codesign	8457	1			T1	1		T3	38		T4	20
access_err	owner_sw_cfg	7442	1			T1	3		T2	4		T3	19
access_err	creator_sw_cfg	8138	1			T1	1		T2	7		T3	33
access_err	vendor_test	8063	1			T3	29		T4	5		T8	4
write_blank_err	secret2	11	1			T14	1		T268	1		T270	1
write_blank_err	secret1	27	1			T70	1		T148	1		T267	1
write_blank_err	secret0	34	1			T170	1		T172	1		T70	2
write_blank_err	hw_cfg1	77	1			T4	1		T11	1		T315	1
write_blank_err	hw_cfg0	23	1			T5	1		T316	1		T135	1
write_blank_err	rot_creator_auth_state	139	1			T170	3		T309	1		T317	1
write_blank_err	rot_creator_auth_codesign	40	1			T10	1		T316	1		T318	2
write_blank_err	owner_sw_cfg	18	1			T172	2		T188	3		T319	1
write_blank_err	creator_sw_cfg	15	1			T135	6		T320	1		T321	2
write_blank_err	vendor_test	26	1			T14	1		T70	1		T135	1
ecc_uncorr_err	secret2	4009	1			T121	21		T111	96		T14	136
ecc_uncorr_err	secret1	9649	1			T111	86		T144	34		T171	45
ecc_uncorr_err	secret0	12754	1			T121	37		T111	50		T144	71
ecc_uncorr_err	hw_cfg1	23411	1			T4	390		T144	74		T11	405
ecc_uncorr_err	hw_cfg0	6870	1			T5	384		T121	20		T197	31
ecc_uncorr_err	rot_creator_auth_state	6865	1			T111	48		T144	41		T171	32
ecc_uncorr_err	rot_creator_auth_codesign	1390	1			T10	152		T111	52		T322	11
ecc_uncorr_err	owner_sw_cfg	1157	1			T121	58		T144	36		T216	15
ecc_uncorr_err	creator_sw_cfg	1029	1			T121	15		T144	38		T171	57
ecc_corr_err	secret2	83	1			T171	1		T199	1		T209	5
ecc_corr_err	secret1	155	1			T121	1		T171	5		T69	5
ecc_corr_err	secret0	182	1			T144	1		T197	3		T69	4
ecc_corr_err	hw_cfg1	347	1			T111	3		T197	6		T69	10
ecc_corr_err	hw_cfg0	272	1			T121	3		T144	1		T69	5
ecc_corr_err	rot_creator_auth_state	117	1			T111	5		T69	3		T199	1
ecc_corr_err	rot_creator_auth_codesign	98	1			T111	1		T144	3		T69	2
ecc_corr_err	owner_sw_cfg	126	1			T111	4		T144	1		T45	1
ecc_corr_err	creator_sw_cfg	109	1			T121	3		T111	2		T171	3
no_err	secret2	5596	1			T1	3		T2	6		T3	17
no_err	secret1	9311	1			T1	1		T2	2		T3	54
no_err	secret0	8870	1			T1	3		T2	10		T3	44
no_err	hw_cfg1	11163	1			T1	6		T2	6		T3	41
no_err	hw_cfg0	13129	1			T1	13		T2	3		T3	39
no_err	rot_creator_auth_state	9114	1			T1	3		T2	9		T3	27
no_err	rot_creator_auth_codesign	9091	1			T1	11		T2	6		T3	47
no_err	owner_sw_cfg	9661	1			T1	6		T2	7		T3	27
no_err	creator_sw_cfg	9084	1			T1	10		T2	2		T3	49
no_err	vendor_test	10726	1			T2	8		T3	21		T4	32

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded