SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 45861 | 1 | T3 | 302 | T5 | 66 | T9 | 2 | ||||
access_err | 64422 | 1 | T9 | 2 | T6 | 12 | T53 | 13 | ||||
write_blank_err | 331 | 1 | T6 | 1 | T8 | 4 | T14 | 1 | ||||
ecc_uncorr_err | 57782 | 1 | T5 | 310 | T9 | 9 | T6 | 110 | ||||
ecc_corr_err | 1428 | 1 | T5 | 11 | T9 | 1 | T113 | 2 | ||||
no_err | 92598 | 1 | T1 | 28 | T4 | 2 | T5 | 20 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 659 | 1 | T6 | 10 | T8 | 13 | T14 | 10 | ||||
secret2 | 25068 | 1 | T1 | 4 | T4 | 1 | T53 | 9 | ||||
secret1 | 27732 | 1 | T1 | 1 | T3 | 302 | T5 | 3 | ||||
secret0 | 31119 | 1 | T1 | 4 | T5 | 41 | T9 | 6 | ||||
hw_cfg1 | 33513 | 1 | T1 | 3 | T5 | 78 | T6 | 1 | ||||
hw_cfg0 | 24849 | 1 | T1 | 1 | T4 | 1 | T6 | 4 | ||||
rot_creator_auth_state | 20563 | 1 | T1 | 2 | T5 | 44 | T9 | 2 | ||||
rot_creator_auth_codesign | 24414 | 1 | T1 | 5 | T5 | 116 | T9 | 11 | ||||
owner_sw_cfg | 22556 | 1 | T1 | 2 | T5 | 111 | T9 | 7 | ||||
creator_sw_cfg | 23632 | 1 | T1 | 2 | T5 | 4 | T6 | 6 | ||||
vendor_test | 28317 | 1 | T1 | 4 | T5 | 10 | T9 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 2199 | 1 | T372 | 25 | T373 | 176 | T20 | 312 | ||||
fsm_err | secret1 | 4001 | 1 | T3 | 302 | T71 | 147 | T374 | 274 | ||||
fsm_err | secret0 | 3395 | 1 | T5 | 34 | T144 | 181 | T184 | 187 | ||||
fsm_err | hw_cfg1 | 2542 | 1 | T168 | 219 | T146 | 123 | T219 | 30 | ||||
fsm_err | hw_cfg0 | 4100 | 1 | T109 | 74 | T268 | 285 | T169 | 285 | ||||
fsm_err | rot_creator_auth_state | 3545 | 1 | T121 | 86 | T113 | 58 | T104 | 10 | ||||
fsm_err | rot_creator_auth_codesign | 5329 | 1 | T269 | 399 | T223 | 35 | T375 | 109 | ||||
fsm_err | owner_sw_cfg | 4537 | 1 | T5 | 32 | T9 | 2 | T216 | 518 | ||||
fsm_err | creator_sw_cfg | 5585 | 1 | T10 | 89 | T376 | 77 | T70 | 136 | ||||
fsm_err | vendor_test | 10628 | 1 | T138 | 114 | T81 | 153 | T145 | 69 | ||||
access_err | life_cycle | 659 | 1 | T6 | 10 | T8 | 13 | T14 | 10 | ||||
access_err | secret2 | 11066 | 1 | T30 | 39 | T31 | 6 | T65 | 15 | ||||
access_err | secret1 | 5913 | 1 | T53 | 1 | T30 | 20 | T31 | 6 | ||||
access_err | secret0 | 4727 | 1 | T9 | 2 | T30 | 14 | T113 | 1 | ||||
access_err | hw_cfg1 | 1293 | 1 | T30 | 9 | T31 | 2 | T65 | 3 | ||||
access_err | hw_cfg0 | 2411 | 1 | T30 | 16 | T31 | 5 | T32 | 11 | ||||
access_err | rot_creator_auth_state | 6395 | 1 | T53 | 4 | T30 | 47 | T31 | 5 | ||||
access_err | rot_creator_auth_codesign | 8597 | 1 | T53 | 1 | T30 | 44 | T31 | 4 | ||||
access_err | owner_sw_cfg | 7280 | 1 | T6 | 1 | T30 | 38 | T31 | 5 | ||||
access_err | creator_sw_cfg | 8379 | 1 | T53 | 2 | T30 | 48 | T31 | 12 | ||||
access_err | vendor_test | 7702 | 1 | T6 | 1 | T53 | 5 | T30 | 67 | ||||
write_blank_err | secret2 | 14 | 1 | T140 | 1 | T250 | 2 | T377 | 1 | ||||
write_blank_err | secret1 | 21 | 1 | T8 | 1 | T14 | 1 | T378 | 1 | ||||
write_blank_err | secret0 | 33 | 1 | T6 | 1 | T153 | 1 | T109 | 1 | ||||
write_blank_err | hw_cfg1 | 54 | 1 | T8 | 1 | T176 | 1 | T261 | 2 | ||||
write_blank_err | hw_cfg0 | 19 | 1 | T8 | 1 | T379 | 1 | T380 | 1 | ||||
write_blank_err | rot_creator_auth_state | 87 | 1 | T8 | 1 | T176 | 1 | T16 | 1 | ||||
write_blank_err | rot_creator_auth_codesign | 36 | 1 | T381 | 1 | T246 | 2 | T382 | 1 | ||||
write_blank_err | owner_sw_cfg | 34 | 1 | T176 | 1 | T261 | 4 | T383 | 2 | ||||
write_blank_err | creator_sw_cfg | 17 | 1 | T16 | 1 | T379 | 4 | T384 | 1 | ||||
write_blank_err | vendor_test | 16 | 1 | T261 | 1 | T381 | 1 | T246 | 1 | ||||
ecc_uncorr_err | secret2 | 6448 | 1 | T385 | 62 | T250 | 1007 | T377 | 449 | ||||
ecc_uncorr_err | secret1 | 8216 | 1 | T113 | 133 | T8 | 140 | T14 | 568 | ||||
ecc_uncorr_err | secret0 | 13961 | 1 | T6 | 110 | T113 | 68 | T153 | 383 | ||||
ecc_uncorr_err | hw_cfg1 | 18412 | 1 | T5 | 76 | T175 | 29 | T176 | 537 | ||||
ecc_uncorr_err | hw_cfg0 | 5560 | 1 | T113 | 142 | T145 | 71 | T223 | 38 | ||||
ecc_uncorr_err | rot_creator_auth_state | 1851 | 1 | T5 | 41 | T113 | 65 | T223 | 64 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 997 | 1 | T5 | 115 | T9 | 9 | T113 | 66 | ||||
ecc_uncorr_err | owner_sw_cfg | 1276 | 1 | T5 | 78 | T145 | 143 | T175 | 37 | ||||
ecc_uncorr_err | creator_sw_cfg | 1061 | 1 | T175 | 34 | T16 | 340 | T223 | 30 | ||||
ecc_corr_err | secret2 | 67 | 1 | T31 | 5 | T56 | 2 | T385 | 1 | ||||
ecc_corr_err | secret1 | 131 | 1 | T5 | 3 | T31 | 1 | T145 | 3 | ||||
ecc_corr_err | secret0 | 142 | 1 | T5 | 1 | T113 | 1 | T145 | 2 | ||||
ecc_corr_err | hw_cfg1 | 304 | 1 | T5 | 1 | T31 | 3 | T8 | 1 | ||||
ecc_corr_err | hw_cfg0 | 288 | 1 | T31 | 2 | T8 | 2 | T77 | 1 | ||||
ecc_corr_err | rot_creator_auth_state | 130 | 1 | T5 | 2 | T9 | 1 | T31 | 8 | ||||
ecc_corr_err | rot_creator_auth_codesign | 116 | 1 | T31 | 4 | T77 | 2 | T56 | 8 | ||||
ecc_corr_err | owner_sw_cfg | 122 | 1 | T5 | 1 | T113 | 1 | T31 | 3 | ||||
ecc_corr_err | creator_sw_cfg | 128 | 1 | T5 | 3 | T31 | 4 | T77 | 4 | ||||
no_err | secret2 | 5274 | 1 | T1 | 4 | T4 | 1 | T53 | 9 | ||||
no_err | secret1 | 9450 | 1 | T1 | 1 | T6 | 3 | T12 | 4 | ||||
no_err | secret0 | 8861 | 1 | T1 | 4 | T5 | 6 | T9 | 4 | ||||
no_err | hw_cfg1 | 10908 | 1 | T1 | 3 | T5 | 1 | T6 | 1 | ||||
no_err | hw_cfg0 | 12471 | 1 | T1 | 1 | T4 | 1 | T6 | 4 | ||||
no_err | rot_creator_auth_state | 8555 | 1 | T1 | 2 | T5 | 1 | T9 | 1 | ||||
no_err | rot_creator_auth_codesign | 9339 | 1 | T1 | 5 | T5 | 1 | T9 | 2 | ||||
no_err | owner_sw_cfg | 9307 | 1 | T1 | 2 | T9 | 5 | T6 | 4 | ||||
no_err | creator_sw_cfg | 8462 | 1 | T1 | 2 | T5 | 1 | T6 | 6 | ||||
no_err | vendor_test | 9971 | 1 | T1 | 4 | T5 | 10 | T9 | 1 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |