Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

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Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	0	5	100.00
Crosses	6	0	6	100.00

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
dai_access_cmd	3	0	3	100.00	100	1	1	0
lc_creator_seed_sw_rw_en	2	0	2	100.00	100	1	1	2

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_access_secret2	6	0	6	100.00	100	1	1	0

Summary for Variable dai_access_cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for dai_access_cmd

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
dai_digest	2426	1			T7	1		T4	4		T5	16
dai_wr	4359	1			T1	3		T3	3		T7	1
dai_rd	7375	1			T1	3		T3	3		T7	1

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Summary for Variable lc_creator_seed_sw_rw_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_creator_seed_sw_rw_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6475

1

T4

8

T5

14

T6

28

auto[1]

7685

1

T1

6

T3

6

T7

3

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Summary for Cross dai_access_secret2

Samples crossed: lc_creator_seed_sw_rw_en dai_access_cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	6	0	6	100.00

Automatically Generated Cross Bins for dai_access_secret2

Bins

lc_creator_seed_sw_rw_en	dai_access_cmd	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	dai_digest	1364	1			T4	4		T5	9		T6	8
auto[0]	dai_wr	1634	1			T5	2		T6	8		T12	2
auto[0]	dai_rd	3477	1			T4	4		T5	3		T6	12
auto[1]	dai_digest	1062	1			T7	1		T5	7		T6	8
auto[1]	dai_wr	2725	1			T1	3		T3	3		T7	1
auto[1]	dai_rd	3898	1			T1	3		T3	3		T7	1