Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	53892	1			T10	538		T5	37		T6	239
access_err	60623	1			T4	43		T5	261		T6	219
write_blank_err	410	1			T6	1		T108	12		T8	2
ecc_uncorr_err	58230	1			T6	469		T108	616		T8	472
ecc_corr_err	1121	1			T108	3		T44	13		T143	14
no_err	92490	1			T4	99		T10	1		T5	346

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	684	1			T6	4		T8	4		T9	2
secret2	26064	1			T4	26		T5	60		T6	51
secret1	27657	1			T4	5		T5	69		T6	45
secret0	32602	1			T4	13		T5	45		T6	48
hw_cfg1	31462	1			T4	4		T5	54		T6	504
hw_cfg0	29237	1			T4	10		T5	89		T6	52
rot_creator_auth_state	24278	1			T4	14		T5	62		T6	118
rot_creator_auth_codesign	19946	1			T4	20		T5	50		T6	65
owner_sw_cfg	22084	1			T4	26		T10	538		T5	67
creator_sw_cfg	20091	1			T4	14		T5	73		T6	52
vendor_test	32661	1			T4	10		T10	1		T5	75

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	4301	1			T172	4		T345	69		T19	287
fsm_err	secret1	4042	1			T8	118		T16	132		T207	91
fsm_err	secret0	4294	1			T123	68		T146	166		T346	14
fsm_err	hw_cfg1	5272	1			T19	25		T347	324		T348	455
fsm_err	hw_cfg0	6624	1			T18	312		T249	226		T147	72
fsm_err	rot_creator_auth_state	5665	1			T6	65		T211	152		T16	473
fsm_err	rot_creator_auth_codesign	1990	1			T143	24		T275	602		T349	90
fsm_err	owner_sw_cfg	3634	1			T10	538		T143	57		T163	46
fsm_err	creator_sw_cfg	2864	1			T5	37		T109	28		T180	150
fsm_err	vendor_test	15206	1			T6	174		T112	424		T9	168
access_err	life_cycle	684	1			T6	4		T8	4		T9	2
access_err	secret2	10927	1			T4	11		T5	33		T6	39
access_err	secret1	5742	1			T4	3		T5	47		T6	24
access_err	secret0	4484	1			T4	1		T5	31		T6	6
access_err	hw_cfg1	1320	1			T5	4		T6	3		T12	4
access_err	hw_cfg0	2236	1			T4	1		T5	20		T6	13
access_err	rot_creator_auth_state	5751	1			T4	7		T5	15		T6	19
access_err	rot_creator_auth_codesign	7787	1			T4	8		T5	22		T6	28
access_err	owner_sw_cfg	6880	1			T4	4		T5	40		T6	24
access_err	creator_sw_cfg	7606	1			T4	5		T5	14		T6	30
access_err	vendor_test	7206	1			T4	3		T5	35		T6	29
write_blank_err	secret2	11	1			T350	1		T250	1		T279	1
write_blank_err	secret1	27	1			T8	1		T162	1		T16	1
write_blank_err	secret0	42	1			T108	1		T182	1		T351	1
write_blank_err	hw_cfg1	43	1			T6	1		T108	1		T18	1
write_blank_err	hw_cfg0	19	1			T108	1		T110	1		T16	1
write_blank_err	rot_creator_auth_state	136	1			T108	7		T9	1		T162	3
write_blank_err	rot_creator_auth_codesign	57	1			T8	1		T162	2		T107	1
write_blank_err	owner_sw_cfg	24	1			T147	1		T250	1		T352	1
write_blank_err	creator_sw_cfg	31	1			T18	1		T353	1		T354	3
write_blank_err	vendor_test	20	1			T108	2		T241	1		T250	1
ecc_uncorr_err	secret2	5327	1			T143	32		T163	50		T165	75
ecc_uncorr_err	secret1	8546	1			T8	472		T162	113		T16	507
ecc_uncorr_err	secret0	14863	1			T108	616		T182	195		T184	37
ecc_uncorr_err	hw_cfg1	14052	1			T6	469		T163	40		T18	646
ecc_uncorr_err	hw_cfg0	7724	1			T110	200		T143	34		T163	50
ecc_uncorr_err	rot_creator_auth_state	3962	1			T9	512		T163	41		T18	434
ecc_uncorr_err	rot_creator_auth_codesign	896	1			T355	47		T356	19		T159	152
ecc_uncorr_err	owner_sw_cfg	1886	1			T143	32		T173	57		T355	90
ecc_uncorr_err	creator_sw_cfg	974	1			T143	27		T165	65		T172	5
ecc_corr_err	secret2	53	1			T184	1		T172	1		T357	1
ecc_corr_err	secret1	100	1			T44	3		T143	1		T163	1
ecc_corr_err	secret0	115	1			T143	5		T69	1		T70	1
ecc_corr_err	hw_cfg1	190	1			T108	2		T44	4		T143	5
ecc_corr_err	hw_cfg0	219	1			T108	1		T44	5		T143	1
ecc_corr_err	rot_creator_auth_state	158	1			T69	3		T52	3		T315	5
ecc_corr_err	rot_creator_auth_codesign	94	1			T44	1		T52	3		T165	1
ecc_corr_err	owner_sw_cfg	100	1			T163	1		T52	2		T172	2
ecc_corr_err	creator_sw_cfg	92	1			T143	2		T172	1		T70	2
no_err	secret2	5445	1			T4	15		T5	27		T6	12
no_err	secret1	9200	1			T4	2		T5	22		T6	21
no_err	secret0	8804	1			T4	12		T5	14		T6	42
no_err	hw_cfg1	10585	1			T4	4		T5	50		T6	31
no_err	hw_cfg0	12415	1			T4	9		T5	69		T6	39
no_err	rot_creator_auth_state	8606	1			T4	7		T5	47		T6	34
no_err	rot_creator_auth_codesign	9122	1			T4	12		T5	28		T6	37
no_err	owner_sw_cfg	9560	1			T4	22		T5	27		T6	39
no_err	creator_sw_cfg	8524	1			T4	9		T5	22		T6	22
no_err	vendor_test	10229	1			T4	7		T10	1		T5	40

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded