Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	50970	1			T1	186		T2	159		T5	149
access_err	62568	1			T1	14		T2	9		T3	20
write_blank_err	495	1			T3	13		T9	1		T16	7
ecc_uncorr_err	76000	1			T3	407		T9	439		T16	1617
ecc_corr_err	1515	1			T70	24		T71	8		T16	1
no_err	88803	1			T1	31		T2	35		T3	46

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	798	1			T3	14		T9	5		T16	9
secret2	26031	1			T1	5		T2	8		T3	4
secret1	32937	1			T1	3		T2	4		T3	2
secret0	35957	1			T1	186		T2	3		T10	2
hw_cfg1	42297	1			T1	4		T3	1		T5	151
hw_cfg0	22540	1			T1	7		T2	2		T3	412
rot_creator_auth_state	23977	1			T1	11		T2	164		T3	12
rot_creator_auth_codesign	23017	1			T1	2		T2	6		T3	13
owner_sw_cfg	20525	1			T1	7		T2	9		T3	14
creator_sw_cfg	20181	1			T1	4		T2	3		T3	12
vendor_test	32091	1			T1	2		T2	4		T3	2

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	5934	1			T16	64		T152	210		T21	135
fsm_err	secret1	6106	1			T119	61		T231	456		T20	133
fsm_err	secret0	3181	1			T1	186		T14	64		T119	132
fsm_err	hw_cfg1	3188	1			T5	149		T344	245		T345	297
fsm_err	hw_cfg0	5369	1			T242	59		T244	250		T100	56
fsm_err	rot_creator_auth_state	4326	1			T2	159		T119	544		T153	72
fsm_err	rot_creator_auth_codesign	4964	1			T150	234		T246	94		T153	30
fsm_err	owner_sw_cfg	1233	1			T346	195		T247	50		T169	55
fsm_err	creator_sw_cfg	2162	1			T236	73		T168	2		T347	17
fsm_err	vendor_test	14507	1			T70	125		T71	15		T8	220
access_err	life_cycle	798	1			T3	14		T9	5		T16	9
access_err	secret2	10765	1			T1	5		T2	4		T10	2
access_err	secret1	6203	1			T6	2		T7	5		T31	22
access_err	secret0	4966	1			T6	2		T7	5		T70	2
access_err	hw_cfg1	1181	1			T5	1		T10	3		T7	1
access_err	hw_cfg0	2092	1			T6	2		T71	2		T31	12
access_err	rot_creator_auth_state	5868	1			T1	2		T3	2		T6	3
access_err	rot_creator_auth_codesign	7990	1			T3	2		T10	3		T7	2
access_err	owner_sw_cfg	7144	1			T1	5		T2	5		T10	1
access_err	creator_sw_cfg	7928	1			T1	2		T3	1		T70	12
access_err	vendor_test	7633	1			T3	1		T10	4		T70	3
write_blank_err	secret2	15	1			T241	1		T135	1		T348	1
write_blank_err	secret1	31	1			T16	1		T157	1		T40	1
write_blank_err	secret0	47	1			T156	1		T108	3		T119	3
write_blank_err	hw_cfg1	80	1			T9	1		T16	2		T108	2
write_blank_err	hw_cfg0	9	1			T3	1		T173	1		T138	1
write_blank_err	rot_creator_auth_state	157	1			T3	4		T16	1		T156	1
write_blank_err	rot_creator_auth_codesign	80	1			T3	5		T16	2		T157	7
write_blank_err	owner_sw_cfg	41	1			T21	5		T256	1		T349	1
write_blank_err	creator_sw_cfg	10	1			T3	3		T157	1		T350	1
write_blank_err	vendor_test	25	1			T16	1		T108	1		T351	2
ecc_uncorr_err	secret2	4208	1			T153	40		T241	210		T135	392
ecc_uncorr_err	secret1	11816	1			T16	551		T157	182		T158	24
ecc_uncorr_err	secret0	19429	1			T156	563		T108	1671		T158	16
ecc_uncorr_err	hw_cfg1	27097	1			T9	439		T16	474		T108	565
ecc_uncorr_err	hw_cfg0	2974	1			T3	407		T158	39		T159	20
ecc_uncorr_err	rot_creator_auth_state	4874	1			T16	592		T108	608		T158	12
ecc_uncorr_err	rot_creator_auth_codesign	1158	1			T159	22		T155	100		T169	81
ecc_uncorr_err	owner_sw_cfg	2811	1			T158	11		T159	21		T256	651
ecc_uncorr_err	creator_sw_cfg	1633	1			T159	54		T155	129		T352	39
ecc_corr_err	secret2	70	1			T158	2		T159	1		T54	7
ecc_corr_err	secret1	148	1			T70	2		T41	1		T159	1
ecc_corr_err	secret0	175	1			T70	1		T41	3		T158	1
ecc_corr_err	hw_cfg1	224	1			T70	2		T71	2		T16	1
ecc_corr_err	hw_cfg0	291	1			T70	17		T71	3		T41	6
ecc_corr_err	rot_creator_auth_state	143	1			T41	5		T158	2		T153	6
ecc_corr_err	rot_creator_auth_codesign	177	1			T70	2		T71	3		T41	2
ecc_corr_err	owner_sw_cfg	121	1			T158	2		T159	2		T153	2
ecc_corr_err	creator_sw_cfg	166	1			T158	4		T32	1		T130	4
no_err	secret2	5039	1			T2	4		T3	4		T7	3
no_err	secret1	8633	1			T1	3		T2	4		T3	2
no_err	secret0	8159	1			T2	3		T10	2		T6	1
no_err	hw_cfg1	10527	1			T1	4		T3	1		T5	1
no_err	hw_cfg0	11805	1			T1	7		T2	2		T3	4
no_err	rot_creator_auth_state	8609	1			T1	9		T2	5		T3	6
no_err	rot_creator_auth_codesign	8648	1			T1	2		T2	6		T3	6
no_err	owner_sw_cfg	9175	1			T1	2		T2	4		T3	14
no_err	creator_sw_cfg	8282	1			T1	2		T2	3		T3	8
no_err	vendor_test	9926	1			T1	2		T2	4		T3	1

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded