Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	50166	1			T4	647		T6	513		T42	65
access_err	64202	1			T3	11		T5	8		T6	375
write_blank_err	444	1			T3	1		T6	3		T8	1
ecc_uncorr_err	69742	1			T3	428		T6	636		T8	574
ecc_corr_err	1342	1			T64	8		T34	5		T129	4
no_err	93745	1			T3	43		T5	18		T9	8

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	693	1			T3	4		T6	2		T8	2
secret2	26543	1			T9	1		T6	90		T7	4
secret1	34057	1			T3	4		T5	6		T9	1
secret0	38178	1			T3	4		T4	647		T5	4
hw_cfg1	33250	1			T3	2		T6	576		T7	2
hw_cfg0	24180	1			T3	438		T5	2		T9	1
rot_creator_auth_state	23450	1			T5	3		T6	127		T7	5
rot_creator_auth_codesign	22792	1			T3	5		T5	2		T6	109
owner_sw_cfg	19961	1			T3	9		T9	2		T6	118
creator_sw_cfg	22902	1			T5	4		T9	2		T6	103
vendor_test	33635	1			T3	17		T5	5		T6	95

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3947	1			T14	43		T96	157		T240	387
fsm_err	secret1	4385	1			T265	127		T191	2		T263	182
fsm_err	secret0	4189	1			T4	647		T108	76		T130	349
fsm_err	hw_cfg1	4272	1			T6	513		T64	12		T249	296
fsm_err	hw_cfg0	3344	1			T366	332		T247	134		T219	98
fsm_err	rot_creator_auth_state	2811	1			T66	357		T282	46		T95	45
fsm_err	rot_creator_auth_codesign	4222	1			T12	418		T266	365		T147	23
fsm_err	owner_sw_cfg	2234	1			T33	196		T193	334		T147	10
fsm_err	creator_sw_cfg	4917	1			T64	14		T188	391		T147	21
fsm_err	vendor_test	15845	1			T42	65		T34	13		T109	267
access_err	life_cycle	693	1			T3	4		T6	2		T8	2
access_err	secret2	11128	1			T6	78		T64	3		T26	10
access_err	secret1	6360	1			T26	10		T34	4		T13	1
access_err	secret0	4987	1			T3	1		T5	1		T6	2
access_err	hw_cfg1	1414	1			T6	6		T7	2		T26	6
access_err	hw_cfg0	2364	1			T64	2		T26	2		T34	2
access_err	rot_creator_auth_state	6289	1			T5	2		T6	86		T26	9
access_err	rot_creator_auth_codesign	8056	1			T6	55		T26	12		T34	2
access_err	owner_sw_cfg	7068	1			T3	6		T6	65		T35	5
access_err	creator_sw_cfg	8240	1			T6	33		T7	1		T26	8
access_err	vendor_test	7603	1			T5	5		T6	48		T26	7
write_blank_err	secret2	14	1			T8	1		T133	1		T130	1
write_blank_err	secret1	30	1			T232	1		T189	1		T191	1
write_blank_err	secret0	48	1			T6	1		T129	2		T179	1
write_blank_err	hw_cfg1	59	1			T133	1		T98	2		T194	1
write_blank_err	hw_cfg0	19	1			T3	1		T133	1		T191	1
write_blank_err	rot_creator_auth_state	155	1			T6	2		T179	1		T232	5
write_blank_err	rot_creator_auth_codesign	52	1			T232	3		T14	1		T191	2
write_blank_err	owner_sw_cfg	31	1			T232	3		T191	1		T367	10
write_blank_err	creator_sw_cfg	6	1			T232	1		T259	1		T255	1
write_blank_err	vendor_test	30	1			T179	1		T232	4		T133	2
ecc_uncorr_err	secret2	5686	1			T8	574		T133	128		T130	518
ecc_uncorr_err	secret1	13736	1			T232	654		T189	113		T191	378
ecc_uncorr_err	secret0	20081	1			T6	636		T64	16		T129	449
ecc_uncorr_err	hw_cfg1	16195	1			T64	7		T133	321		T98	420
ecc_uncorr_err	hw_cfg0	5641	1			T3	428		T192	465		T147	35
ecc_uncorr_err	rot_creator_auth_state	5231	1			T64	14		T133	457		T147	24
ecc_uncorr_err	rot_creator_auth_codesign	1682	1			T198	44		T199	75		T368	9
ecc_uncorr_err	owner_sw_cfg	775	1			T64	20		T168	67		T369	68
ecc_uncorr_err	creator_sw_cfg	715	1			T64	19		T147	22		T370	80
ecc_corr_err	secret2	95	1			T34	2		T44	6		T370	1
ecc_corr_err	secret1	106	1			T77	2		T45	1		T147	1
ecc_corr_err	secret0	120	1			T34	1		T129	4		T76	1
ecc_corr_err	hw_cfg1	263	1			T64	3		T67	2		T76	2
ecc_corr_err	hw_cfg0	258	1			T133	4		T44	11		T77	8
ecc_corr_err	rot_creator_auth_state	142	1			T64	1		T34	1		T232	3
ecc_corr_err	rot_creator_auth_codesign	122	1			T64	1		T76	2		T44	10
ecc_corr_err	owner_sw_cfg	113	1			T64	1		T34	1		T77	1
ecc_corr_err	creator_sw_cfg	123	1			T64	2		T76	2		T44	10
no_err	secret2	5673	1			T9	1		T6	12		T7	4
no_err	secret1	9440	1			T3	4		T5	6		T9	1
no_err	secret0	8753	1			T3	3		T5	3		T9	1
no_err	hw_cfg1	11047	1			T3	2		T6	57		T8	2
no_err	hw_cfg0	12554	1			T3	9		T5	2		T9	1
no_err	rot_creator_auth_state	8822	1			T5	1		T6	39		T7	5
no_err	rot_creator_auth_codesign	8658	1			T3	5		T5	2		T6	54
no_err	owner_sw_cfg	9740	1			T3	3		T9	2		T6	53
no_err	creator_sw_cfg	8901	1			T5	4		T9	2		T6	70
no_err	vendor_test	10157	1			T3	17		T6	47		T7	1

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded