Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv



Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
secret1_lock 2 0 2 100.00 100 1 1 2
sram_index 4 0 4 100.00 100 1 1 0


Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sram_req_lock_cross 8 0 8 100.00 100 1 1 0


Summary for Variable secret1_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for secret1_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1641 1 T6 9 T65 6 T112 1
auto[1] 1000 1 T65 38 T103 13 T127 22



Summary for Variable sram_index

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for sram_index

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sram_key[0x0] 174 1 T65 2 T103 6 T133 11
sram_key[0x1] 738 1 T6 2 T65 3 T232 1
sram_key[0x2] 820 1 T6 3 T65 17 T232 1
sram_key[0x3] 909 1 T6 4 T65 22 T112 1



Summary for Cross sram_req_lock_cross

Samples crossed: sram_index secret1_lock
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for sram_req_lock_cross

Bins
sram_indexsecret1_lockCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sram_key[0x0] auto[0] 119 1 T65 1 T103 1 T133 2
sram_key[0x0] auto[1] 55 1 T65 1 T103 5 T133 9
sram_key[0x1] auto[0] 441 1 T6 2 T232 1 T103 1
sram_key[0x1] auto[1] 297 1 T65 3 T127 8 T133 33
sram_key[0x2] auto[0] 512 1 T6 3 T65 2 T232 1
sram_key[0x2] auto[1] 308 1 T65 15 T103 3 T127 5
sram_key[0x3] auto[0] 569 1 T6 4 T65 3 T112 1
sram_key[0x3] auto[1] 340 1 T65 19 T103 5 T127 9

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%