Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	45963	1			T8	191		T7	119		T14	675
access_err	62933	1			T1	14		T2	6		T3	101
write_blank_err	391	1			T5	8		T6	2		T7	1
ecc_uncorr_err	72483	1			T5	133		T6	1001		T7	440
ecc_corr_err	1392	1			T69	75		T40	55		T139	8
no_err	91649	1			T1	27		T2	19		T3	61

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	679	1			T5	12		T6	5		T14	12
secret2	24758	1			T1	5		T2	2		T3	8
secret1	32642	1			T1	6		T2	1		T3	19
secret0	38261	1			T1	3		T3	14		T5	142
hw_cfg1	36318	1			T1	8		T2	3		T3	10
hw_cfg0	26235	1			T1	3		T2	8		T3	17
rot_creator_auth_state	21487	1			T1	3		T3	18		T5	17
rot_creator_auth_codesign	20461	1			T1	3		T2	4		T3	13
owner_sw_cfg	20236	1			T2	2		T3	21		T8	5
creator_sw_cfg	22720	1			T1	6		T2	5		T3	18
vendor_test	31014	1			T1	4		T3	24		T4	2

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2345	1			T8	191		T78	153		T329	120
fsm_err	secret1	5949	1			T14	1		T78	255		T218	165
fsm_err	secret0	3947	1			T174	582		T150	258		T221	178
fsm_err	hw_cfg1	2284	1			T7	119		T267	209		T330	579
fsm_err	hw_cfg0	5550	1			T218	24		T241	136		T224	132
fsm_err	rot_creator_auth_state	3121	1			T331	340		T332	104		T333	173
fsm_err	rot_creator_auth_codesign	2539	1			T70	6		T218	70		T146	35
fsm_err	owner_sw_cfg	2450	1			T190	6		T140	42		T334	227
fsm_err	creator_sw_cfg	4389	1			T14	527		T140	32		T335	640
fsm_err	vendor_test	13389	1			T14	147		T16	201		T69	147
access_err	life_cycle	679	1			T5	12		T6	5		T14	12
access_err	secret2	10912	1			T1	3		T2	2		T3	5
access_err	secret1	6025	1			T1	3		T3	15		T12	28
access_err	secret0	4590	1			T3	14		T12	24		T6	4
access_err	hw_cfg1	1289	1			T3	4		T5	1		T11	4
access_err	hw_cfg0	2139	1			T3	12		T12	6		T34	14
access_err	rot_creator_auth_state	6103	1			T1	1		T3	10		T5	6
access_err	rot_creator_auth_codesign	8008	1			T1	1		T2	1		T3	10
access_err	owner_sw_cfg	7374	1			T3	1		T5	2		T12	38
access_err	creator_sw_cfg	8195	1			T1	3		T2	3		T3	16
access_err	vendor_test	7619	1			T1	3		T3	14		T8	1
write_blank_err	secret2	16	1			T65	1		T321	2		T256	1
write_blank_err	secret1	26	1			T246	1		T321	1		T336	1
write_blank_err	secret0	51	1			T5	1		T7	1		T14	1
write_blank_err	hw_cfg1	71	1			T6	2		T104	1		T232	1
write_blank_err	hw_cfg0	15	1			T337	1		T338	1		T339	1
write_blank_err	rot_creator_auth_state	105	1			T5	3		T14	2		T232	3
write_blank_err	rot_creator_auth_codesign	37	1			T229	1		T340	4		T253	1
write_blank_err	owner_sw_cfg	27	1			T5	2		T213	1		T341	1
write_blank_err	creator_sw_cfg	14	1			T5	2		T340	1		T342	2
write_blank_err	vendor_test	29	1			T338	2		T249	1		T342	1
ecc_uncorr_err	secret2	6241	1			T65	705		T167	32		T321	432
ecc_uncorr_err	secret1	11320	1			T140	14		T246	574		T146	40
ecc_uncorr_err	secret0	20941	1			T5	133		T7	440		T14	587
ecc_uncorr_err	hw_cfg1	21469	1			T6	1001		T104	276		T232	614
ecc_uncorr_err	hw_cfg0	5630	1			T140	38		T337	386		T338	386
ecc_uncorr_err	rot_creator_auth_state	3481	1			T139	50		T140	73		T146	41
ecc_uncorr_err	rot_creator_auth_codesign	814	1			T139	37		T133	139		T343	6
ecc_uncorr_err	owner_sw_cfg	1042	1			T139	46		T343	12		T227	2
ecc_uncorr_err	creator_sw_cfg	1545	1			T133	281		T343	12		T344	41
ecc_corr_err	secret2	70	1			T69	5		T40	7		T73	1
ecc_corr_err	secret1	113	1			T69	3		T40	6		T73	2
ecc_corr_err	secret0	184	1			T69	21		T40	7		T73	2
ecc_corr_err	hw_cfg1	252	1			T69	24		T40	5		T139	4
ecc_corr_err	hw_cfg0	270	1			T69	10		T40	20		T73	5
ecc_corr_err	rot_creator_auth_state	129	1			T69	1		T40	1		T139	1
ecc_corr_err	rot_creator_auth_codesign	133	1			T69	6		T40	4		T41	1
ecc_corr_err	owner_sw_cfg	127	1			T69	4		T40	5		T139	2
ecc_corr_err	creator_sw_cfg	114	1			T69	1		T139	1		T57	4
no_err	secret2	5174	1			T1	2		T3	3		T8	1
no_err	secret1	9209	1			T1	3		T2	1		T3	4
no_err	secret0	8548	1			T1	3		T5	8		T11	1
no_err	hw_cfg1	10953	1			T1	8		T2	3		T3	6
no_err	hw_cfg0	12631	1			T1	3		T2	8		T3	5
no_err	rot_creator_auth_state	8548	1			T1	2		T3	8		T5	8
no_err	rot_creator_auth_codesign	8930	1			T1	2		T2	3		T3	3
no_err	owner_sw_cfg	9216	1			T2	2		T3	20		T8	5
no_err	creator_sw_cfg	8463	1			T1	3		T2	2		T3	2
no_err	vendor_test	9977	1			T1	1		T3	10		T4	2

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded