Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	55561	1			T47	59		T4	106		T5	42
access_err	59689	1			T2	305		T3	85		T7	4
write_blank_err	342	1			T4	2		T6	15		T16	3
ecc_uncorr_err	57423	1			T47	58		T4	88		T6	469
ecc_corr_err	1168	1			T47	1		T166	4		T41	48
no_err	88445	1			T1	75		T2	286		T3	81

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	579	1			T4	12		T6	6		T16	3
secret2	23455	1			T1	7		T2	73		T3	22
secret1	27002	1			T1	11		T2	53		T3	22
secret0	35793	1			T1	3		T2	33		T3	16
hw_cfg1	31968	1			T1	10		T2	44		T3	8
hw_cfg0	22085	1			T1	4		T2	73		T3	17
rot_creator_auth_state	23166	1			T1	11		T2	65		T3	10
rot_creator_auth_codesign	22069	1			T1	2		T2	66		T3	20
owner_sw_cfg	22305	1			T1	8		T2	64		T3	15
creator_sw_cfg	21419	1			T1	10		T2	60		T3	14
vendor_test	32787	1			T1	9		T2	60		T3	22

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	5609	1			T157	421		T98	84		T21	364
fsm_err	secret1	3024	1			T47	29		T5	42		T38	53
fsm_err	secret0	6210	1			T15	425		T256	388		T204	193
fsm_err	hw_cfg1	5096	1			T164	19		T354	86		T213	451
fsm_err	hw_cfg0	3377	1			T15	37		T167	341		T251	227
fsm_err	rot_creator_auth_state	3302	1			T4	106		T90	50		T156	54
fsm_err	rot_creator_auth_codesign	4044	1			T156	43		T196	55		T355	143
fsm_err	owner_sw_cfg	4746	1			T90	60		T356	419		T225	37
fsm_err	creator_sw_cfg	4330	1			T87	322		T90	61		T128	32
fsm_err	vendor_test	15823	1			T47	30		T41	189		T70	15
access_err	life_cycle	579	1			T4	12		T6	6		T16	3
access_err	secret2	10461	1			T2	62		T3	20		T7	1
access_err	secret1	5987	1			T2	43		T3	19		T8	8
access_err	secret0	4836	1			T2	19		T3	3		T8	7
access_err	hw_cfg1	1290	1			T3	7		T7	1		T8	2
access_err	hw_cfg0	2104	1			T2	13		T3	7		T7	2
access_err	rot_creator_auth_state	5749	1			T2	29		T3	4		T8	2
access_err	rot_creator_auth_codesign	7512	1			T2	48		T3	6		T8	4
access_err	owner_sw_cfg	6553	1			T2	23		T9	3		T18	2
access_err	creator_sw_cfg	7489	1			T2	35		T3	8		T9	2
access_err	vendor_test	7129	1			T2	33		T3	11		T8	3
write_blank_err	secret2	5	1			T357	1		T220	1		T358	1
write_blank_err	secret1	25	1			T15	1		T220	1		T223	1
write_blank_err	secret0	43	1			T4	1		T6	1		T16	1
write_blank_err	hw_cfg1	44	1			T359	1		T22	1		T352	1
write_blank_err	hw_cfg0	22	1			T360	1		T361	1		T144	1
write_blank_err	rot_creator_auth_state	105	1			T4	1		T6	12		T16	2
write_blank_err	rot_creator_auth_codesign	44	1			T362	1		T144	6		T118	1
write_blank_err	owner_sw_cfg	27	1			T199	1		T220	1		T118	1
write_blank_err	creator_sw_cfg	7	1			T6	2		T118	1		T363	1
write_blank_err	vendor_test	20	1			T352	7		T200	1		T215	1
ecc_uncorr_err	secret2	2150	1			T47	26		T90	62		T128	33
ecc_uncorr_err	secret1	9201	1			T15	314		T128	32		T220	147
ecc_uncorr_err	secret0	16454	1			T4	88		T6	469		T16	677
ecc_uncorr_err	hw_cfg1	15018	1			T128	32		T228	55		T359	545
ecc_uncorr_err	hw_cfg0	4240	1			T228	75		T360	238		T361	182
ecc_uncorr_err	rot_creator_auth_state	5542	1			T47	32		T90	120		T156	41
ecc_uncorr_err	rot_creator_auth_codesign	1780	1			T160	11		T128	24		T362	305
ecc_uncorr_err	owner_sw_cfg	1709	1			T90	62		T220	334		T364	9
ecc_uncorr_err	creator_sw_cfg	1329	1			T90	61		T228	63		T156	47
ecc_corr_err	secret2	72	1			T70	1		T42	6		T228	1
ecc_corr_err	secret1	114	1			T166	2		T42	3		T90	5
ecc_corr_err	secret0	97	1			T166	2		T41	2		T42	5
ecc_corr_err	hw_cfg1	225	1			T41	10		T42	5		T71	4
ecc_corr_err	hw_cfg0	239	1			T41	7		T42	16		T86	2
ecc_corr_err	rot_creator_auth_state	115	1			T41	12		T16	3		T42	3
ecc_corr_err	rot_creator_auth_codesign	116	1			T41	5		T42	4		T71	3
ecc_corr_err	owner_sw_cfg	94	1			T41	8		T42	3		T71	6
ecc_corr_err	creator_sw_cfg	96	1			T47	1		T41	4		T42	3
no_err	secret2	5158	1			T1	7		T2	11		T3	2
no_err	secret1	8651	1			T1	11		T2	10		T3	3
no_err	secret0	8153	1			T1	3		T2	14		T3	13
no_err	hw_cfg1	10295	1			T1	10		T2	44		T3	1
no_err	hw_cfg0	12103	1			T1	4		T2	60		T3	10
no_err	rot_creator_auth_state	8353	1			T1	11		T2	36		T3	6
no_err	rot_creator_auth_codesign	8573	1			T1	2		T2	18		T3	14
no_err	owner_sw_cfg	9176	1			T1	8		T2	41		T3	15
no_err	creator_sw_cfg	8168	1			T1	10		T2	25		T3	6
no_err	vendor_test	9815	1			T1	9		T2	27		T3	11

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded