Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	53273	1			T1	170		T2	151		T9	91
access_err	63094	1			T1	10		T2	27		T9	3
write_blank_err	460	1			T3	7		T6	1		T7	3
ecc_uncorr_err	60534	1			T1	445		T3	702		T6	686
ecc_corr_err	1322	1			T1	13		T2	16		T11	23
no_err	92116	1			T1	26		T2	71		T3	24

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	743	1			T6	2		T7	7		T8	6
secret2	23915	1			T1	134		T2	8		T3	2
secret1	31022	1			T1	188		T2	10		T3	3
secret0	34953	1			T2	11		T3	706		T9	1
hw_cfg1	33887	1			T1	128		T2	14		T3	3
hw_cfg0	22669	1			T2	14		T3	2		T9	6
rot_creator_auth_state	22384	1			T1	69		T2	9		T3	8
rot_creator_auth_codesign	24848	1			T1	63		T2	15		T3	9
owner_sw_cfg	21915	1			T1	67		T2	17		T5	1
creator_sw_cfg	20908	1			T1	4		T2	2		T9	2
vendor_test	33555	1			T1	11		T2	165		T9	96

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3269	1			T12	533		T13	4		T303	38
fsm_err	secret1	6679	1			T1	109		T155	222		T360	614
fsm_err	secret0	4880	1			T156	58		T351	151		T78	123
fsm_err	hw_cfg1	3637	1			T160	142		T167	407		T278	97
fsm_err	hw_cfg0	3193	1			T157	148		T353	85		T276	86
fsm_err	rot_creator_auth_state	2905	1			T223	64		T216	34		T217	63
fsm_err	rot_creator_auth_codesign	6033	1			T1	61		T15	277		T17	16
fsm_err	owner_sw_cfg	3864	1			T361	81		T186	67		T217	54
fsm_err	creator_sw_cfg	3375	1			T352	26		T78	267		T229	5
fsm_err	vendor_test	15438	1			T2	151		T9	91		T11	22
access_err	life_cycle	743	1			T6	2		T7	7		T8	6
access_err	secret2	11129	1			T1	4		T5	1		T11	19
access_err	secret1	6086	1			T5	5		T11	21		T35	26
access_err	secret0	4749	1			T2	5		T9	1		T5	3
access_err	hw_cfg1	1304	1			T2	2		T35	2		T117	1
access_err	hw_cfg0	2033	1			T2	7		T11	4		T35	8
access_err	rot_creator_auth_state	6421	1			T1	4		T35	5		T120	2
access_err	rot_creator_auth_codesign	7734	1			T2	8		T5	7		T11	8
access_err	owner_sw_cfg	6988	1			T1	2		T2	3		T11	9
access_err	creator_sw_cfg	8190	1			T2	2		T5	4		T11	10
access_err	vendor_test	7717	1			T9	2		T11	2		T35	16
write_blank_err	secret2	14	1			T169	1		T362	1		T309	1
write_blank_err	secret1	26	1			T14	1		T363	1		T145	1
write_blank_err	secret0	44	1			T3	1		T8	1		T174	1
write_blank_err	hw_cfg1	63	1			T7	1		T172	1		T173	2
write_blank_err	hw_cfg0	16	1			T6	1		T14	1		T137	2
write_blank_err	rot_creator_auth_state	161	1			T3	2		T8	1		T173	5
write_blank_err	rot_creator_auth_codesign	71	1			T3	4		T7	1		T145	1
write_blank_err	owner_sw_cfg	24	1			T8	3		T302	1		T137	3
write_blank_err	creator_sw_cfg	15	1			T7	1		T175	2		T137	2
write_blank_err	vendor_test	26	1			T173	1		T27	1		T137	1
ecc_uncorr_err	secret2	4151	1			T1	126		T177	24		T181	37
ecc_uncorr_err	secret1	8872	1			T1	64		T115	15		T177	38
ecc_uncorr_err	secret0	16697	1			T3	702		T115	44		T8	630
ecc_uncorr_err	hw_cfg1	17774	1			T1	128		T115	16		T7	643
ecc_uncorr_err	hw_cfg0	4780	1			T6	686		T177	18		T14	113
ecc_uncorr_err	rot_creator_auth_state	4235	1			T1	64		T175	462		T17	46
ecc_uncorr_err	rot_creator_auth_codesign	1732	1			T364	16		T232	40		T230	9
ecc_uncorr_err	owner_sw_cfg	1606	1			T1	63		T115	19		T302	490
ecc_uncorr_err	creator_sw_cfg	687	1			T181	40		T232	4		T216	94
ecc_corr_err	secret2	85	1			T1	1		T2	2		T11	3
ecc_corr_err	secret1	126	1			T1	11		T2	3		T11	1
ecc_corr_err	secret0	125	1			T11	1		T177	3		T69	1
ecc_corr_err	hw_cfg1	272	1			T2	4		T11	3		T115	2
ecc_corr_err	hw_cfg0	239	1			T2	5		T11	2		T137	6
ecc_corr_err	rot_creator_auth_state	129	1			T11	2		T69	1		T357	1
ecc_corr_err	rot_creator_auth_codesign	109	1			T1	1		T2	2		T177	2
ecc_corr_err	owner_sw_cfg	122	1			T11	9		T115	1		T177	1
ecc_corr_err	creator_sw_cfg	115	1			T11	2		T216	1		T230	2
no_err	secret2	5267	1			T1	3		T2	6		T3	2
no_err	secret1	9233	1			T1	4		T2	7		T3	3
no_err	secret0	8458	1			T2	6		T3	3		T5	2
no_err	hw_cfg1	10837	1			T2	8		T3	3		T5	6
no_err	hw_cfg0	12408	1			T2	2		T3	2		T9	6
no_err	rot_creator_auth_state	8533	1			T1	1		T2	9		T3	6
no_err	rot_creator_auth_codesign	9169	1			T1	1		T2	5		T3	5
no_err	owner_sw_cfg	9311	1			T1	2		T2	14		T5	1
no_err	creator_sw_cfg	8526	1			T1	4		T9	2		T10	11
no_err	vendor_test	10374	1			T1	11		T2	14		T9	3

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded