Group : tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
flash_data_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
flash_data_req_during_lc_esc 2 0 2 100.00 100 1 1 0
flash_data_req_during_otbn_req 2 0 2 100.00 100 1 1 2
flash_data_req_during_otp_idle 2 0 2 100.00 100 1 1 2
flash_data_req_during_sram_0_req 2 0 2 100.00 100 1 1 2
flash_data_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable flash_data_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12114 1 T1 93 T2 2 T9 2
auto[1] 982 1 T1 7 T8 8 T14 10



Summary for Variable flash_data_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for flash_data_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 13069 1 T1 100 T2 2 T9 2
lc_esc_on 27 1 T409 1 T37 1 T156 1



Summary for Variable flash_data_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12124 1 T1 75 T2 2 T9 2
auto[1] 972 1 T1 25 T4 1 T8 8



Summary for Variable flash_data_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1901 1 T1 10 T9 1 T4 5
auto[1] 11195 1 T1 90 T2 2 T9 1



Summary for Variable flash_data_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11084 1 T1 74 T2 1 T9 2
auto[1] 2012 1 T1 26 T2 1 T11 6



Summary for Variable flash_data_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12667 1 T1 100 T2 2 T9 2
auto[1] 429 1 T14 4 T37 1 T69 8

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