SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 52591 | 1 | T2 | 33 | T9 | 332 | T4 | 315 | ||||
access_err | 63738 | 1 | T1 | 327 | T4 | 32 | T10 | 4 | ||||
write_blank_err | 358 | 1 | T7 | 2 | T14 | 1 | T146 | 1 | ||||
ecc_uncorr_err | 65743 | 1 | T2 | 26 | T11 | 119 | T7 | 152 | ||||
ecc_corr_err | 1275 | 1 | T2 | 2 | T15 | 2 | T119 | 4 | ||||
no_err | 89494 | 1 | T1 | 264 | T2 | 11 | T4 | 108 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 715 | 1 | T7 | 6 | T14 | 3 | T15 | 13 | ||||
secret2 | 20929 | 1 | T1 | 38 | T2 | 4 | T4 | 24 | ||||
secret1 | 29386 | 1 | T1 | 62 | T2 | 2 | T9 | 332 | ||||
secret0 | 32050 | 1 | T1 | 38 | T4 | 331 | T10 | 5 | ||||
hw_cfg1 | 39917 | 1 | T1 | 46 | T4 | 11 | T10 | 6 | ||||
hw_cfg0 | 30531 | 1 | T1 | 100 | T2 | 2 | T4 | 8 | ||||
rot_creator_auth_state | 21250 | 1 | T1 | 30 | T4 | 19 | T10 | 2 | ||||
rot_creator_auth_codesign | 23331 | 1 | T1 | 65 | T2 | 29 | T4 | 10 | ||||
owner_sw_cfg | 20760 | 1 | T1 | 76 | T4 | 19 | T10 | 1 | ||||
creator_sw_cfg | 21845 | 1 | T1 | 55 | T4 | 9 | T10 | 4 | ||||
vendor_test | 32485 | 1 | T1 | 81 | T2 | 35 | T4 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 1791 | 1 | T164 | 37 | T141 | 75 | T354 | 16 | ||||
fsm_err | secret1 | 4140 | 1 | T9 | 332 | T15 | 535 | T215 | 412 | ||||
fsm_err | secret0 | 3038 | 1 | T4 | 315 | T355 | 400 | T138 | 308 | ||||
fsm_err | hw_cfg1 | 5163 | 1 | T165 | 47 | T356 | 545 | T357 | 381 | ||||
fsm_err | hw_cfg0 | 9455 | 1 | T10 | 292 | T37 | 234 | T358 | 377 | ||||
fsm_err | rot_creator_auth_state | 1980 | 1 | T11 | 44 | T165 | 59 | T203 | 22 | ||||
fsm_err | rot_creator_auth_codesign | 4905 | 1 | T116 | 123 | T169 | 53 | T359 | 587 | ||||
fsm_err | owner_sw_cfg | 2794 | 1 | T246 | 122 | T225 | 55 | T241 | 32 | ||||
fsm_err | creator_sw_cfg | 4236 | 1 | T69 | 9 | T232 | 51 | T258 | 90 | ||||
fsm_err | vendor_test | 15089 | 1 | T2 | 33 | T12 | 395 | T78 | 12 | ||||
access_err | life_cycle | 715 | 1 | T7 | 6 | T14 | 3 | T15 | 13 | ||||
access_err | secret2 | 11016 | 1 | T1 | 31 | T4 | 16 | T34 | 2 | ||||
access_err | secret1 | 6176 | 1 | T1 | 50 | T34 | 6 | T28 | 33 | ||||
access_err | secret0 | 4724 | 1 | T1 | 24 | T10 | 1 | T11 | 1 | ||||
access_err | hw_cfg1 | 1152 | 1 | T1 | 2 | T4 | 1 | T7 | 1 | ||||
access_err | hw_cfg0 | 2009 | 1 | T1 | 20 | T27 | 6 | T28 | 9 | ||||
access_err | rot_creator_auth_state | 6373 | 1 | T1 | 17 | T4 | 4 | T34 | 5 | ||||
access_err | rot_creator_auth_codesign | 8103 | 1 | T1 | 61 | T11 | 3 | T34 | 2 | ||||
access_err | owner_sw_cfg | 7204 | 1 | T1 | 30 | T4 | 8 | T34 | 2 | ||||
access_err | creator_sw_cfg | 8442 | 1 | T1 | 41 | T4 | 1 | T10 | 3 | ||||
access_err | vendor_test | 7824 | 1 | T1 | 51 | T4 | 2 | T34 | 5 | ||||
write_blank_err | secret2 | 6 | 1 | T14 | 1 | T251 | 1 | T326 | 1 | ||||
write_blank_err | secret1 | 23 | 1 | T7 | 1 | T114 | 1 | T117 | 1 | ||||
write_blank_err | secret0 | 39 | 1 | T37 | 1 | T108 | 1 | T347 | 1 | ||||
write_blank_err | hw_cfg1 | 75 | 1 | T146 | 1 | T15 | 2 | T117 | 1 | ||||
write_blank_err | hw_cfg0 | 15 | 1 | T278 | 1 | T343 | 1 | T345 | 1 | ||||
write_blank_err | rot_creator_auth_state | 126 | 1 | T7 | 1 | T15 | 4 | T117 | 1 | ||||
write_blank_err | rot_creator_auth_codesign | 36 | 1 | T15 | 2 | T117 | 1 | T359 | 2 | ||||
write_blank_err | owner_sw_cfg | 12 | 1 | T359 | 2 | T253 | 1 | T360 | 1 | ||||
write_blank_err | creator_sw_cfg | 12 | 1 | T361 | 1 | T362 | 3 | T360 | 1 | ||||
write_blank_err | vendor_test | 14 | 1 | T108 | 1 | T363 | 1 | T364 | 1 | ||||
ecc_uncorr_err | secret2 | 2850 | 1 | T14 | 243 | T169 | 42 | T171 | 117 | ||||
ecc_uncorr_err | secret1 | 9973 | 1 | T7 | 152 | T114 | 627 | T117 | 350 | ||||
ecc_uncorr_err | secret0 | 15552 | 1 | T11 | 47 | T37 | 603 | T108 | 360 | ||||
ecc_uncorr_err | hw_cfg1 | 22706 | 1 | T146 | 217 | T15 | 94 | T117 | 502 | ||||
ecc_uncorr_err | hw_cfg0 | 6386 | 1 | T119 | 5 | T165 | 116 | T171 | 63 | ||||
ecc_uncorr_err | rot_creator_auth_state | 4341 | 1 | T119 | 2 | T169 | 55 | T165 | 53 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 1283 | 1 | T2 | 26 | T11 | 39 | T165 | 68 | ||||
ecc_uncorr_err | owner_sw_cfg | 1711 | 1 | T119 | 8 | T169 | 44 | T178 | 30 | ||||
ecc_uncorr_err | creator_sw_cfg | 941 | 1 | T11 | 33 | T169 | 52 | T165 | 69 | ||||
ecc_corr_err | secret2 | 79 | 1 | T2 | 1 | T124 | 1 | T178 | 1 | ||||
ecc_corr_err | secret1 | 123 | 1 | T2 | 1 | T124 | 3 | T165 | 7 | ||||
ecc_corr_err | secret0 | 173 | 1 | T124 | 1 | T165 | 3 | T170 | 4 | ||||
ecc_corr_err | hw_cfg1 | 275 | 1 | T15 | 2 | T119 | 1 | T124 | 2 | ||||
ecc_corr_err | hw_cfg0 | 203 | 1 | T124 | 2 | T169 | 1 | T170 | 5 | ||||
ecc_corr_err | rot_creator_auth_state | 89 | 1 | T124 | 1 | T165 | 1 | T170 | 4 | ||||
ecc_corr_err | rot_creator_auth_codesign | 111 | 1 | T169 | 2 | T178 | 3 | T165 | 1 | ||||
ecc_corr_err | owner_sw_cfg | 129 | 1 | T119 | 1 | T178 | 1 | T165 | 1 | ||||
ecc_corr_err | creator_sw_cfg | 93 | 1 | T119 | 2 | T68 | 1 | T124 | 8 | ||||
no_err | secret2 | 5187 | 1 | T1 | 7 | T2 | 3 | T4 | 8 | ||||
no_err | secret1 | 8951 | 1 | T1 | 12 | T2 | 1 | T4 | 14 | ||||
no_err | secret0 | 8524 | 1 | T1 | 14 | T4 | 16 | T10 | 4 | ||||
no_err | hw_cfg1 | 10546 | 1 | T1 | 44 | T4 | 10 | T10 | 6 | ||||
no_err | hw_cfg0 | 12463 | 1 | T1 | 80 | T2 | 2 | T4 | 8 | ||||
no_err | rot_creator_auth_state | 8341 | 1 | T1 | 13 | T4 | 15 | T10 | 2 | ||||
no_err | rot_creator_auth_codesign | 8893 | 1 | T1 | 4 | T2 | 3 | T4 | 10 | ||||
no_err | owner_sw_cfg | 8910 | 1 | T1 | 46 | T4 | 11 | T10 | 1 | ||||
no_err | creator_sw_cfg | 8121 | 1 | T1 | 14 | T4 | 8 | T10 | 1 | ||||
no_err | vendor_test | 9558 | 1 | T1 | 30 | T2 | 2 | T4 | 8 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |