Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
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Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv



Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
secret1_lock 2 0 2 100.00 100 1 1 2
sram_index 4 0 4 100.00 100 1 1 0


Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sram_req_lock_cross 8 0 8 100.00 100 1 1 0


Summary for Variable secret1_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for secret1_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1814 1 T2 3 T4 37 T14 41
auto[1] 1411 1 T28 7 T45 11 T38 6



Summary for Variable sram_index

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for sram_index

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sram_key[0x0] 131 1 T14 5 T38 1 T391 2
sram_key[0x1] 1007 1 T2 1 T4 13 T14 8
sram_key[0x2] 1023 1 T2 1 T4 11 T14 13
sram_key[0x3] 1064 1 T2 1 T4 13 T14 15



Summary for Cross sram_req_lock_cross

Samples crossed: sram_index secret1_lock
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for sram_req_lock_cross

Bins
sram_indexsecret1_lockCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sram_key[0x0] auto[0] 76 1 T14 5 T38 1 T406 1
sram_key[0x0] auto[1] 55 1 T391 2 T231 2 T406 4
sram_key[0x1] auto[0] 586 1 T2 1 T4 13 T14 8
sram_key[0x1] auto[1] 421 1 T45 3 T38 2 T136 1
sram_key[0x2] auto[0] 558 1 T2 1 T4 11 T14 13
sram_key[0x2] auto[1] 465 1 T28 4 T45 4 T38 3
sram_key[0x3] auto[0] 594 1 T2 1 T4 13 T14 15
sram_key[0x3] auto[1] 470 1 T28 3 T45 4 T38 1

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