Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
flash_addr_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
flash_addr_req_during_lc_esc	2	0	2	100.00	100	1	1	0
flash_addr_req_during_otbn_req	2	0	2	100.00	100	1	1	2
flash_addr_req_during_otp_idle	2	0	2	100.00	100	1	1	2
flash_addr_req_during_sram_0_req	2	0	2	100.00	100	1	1	2
flash_addr_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable flash_addr_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11578

1

T3

13

T4

4

T5

1

auto[1]

2246

1

T3

1

T4

4

T5

1

---

Summary for Variable flash_addr_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for flash_addr_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

13789

1

T3

14

T4

8

T5

2

lc_esc_on

35

1

T68

1

T96

1

T324

1

---

Summary for Variable flash_addr_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12852

1

T3

14

T4

8

T5

2

auto[1]

972

1

T6

54

T7

6

T25

2

---

Summary for Variable flash_addr_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2093

1

T3

2

T6

10

T7

11

auto[1]

11731

1

T3

12

T4

8

T5

2

---

Summary for Variable flash_addr_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13039

1

T3

14

T4

8

T5

2

auto[1]

785

1

T6

30

T7

2

T25

1

---

Summary for Variable flash_addr_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13450

1

T3

14

T4

8

T5

2

auto[1]

374

1

T6

49

T7

1

T66

8